merge logichelper into last class that uses it
This commit is contained in:
Torsten Ruger
parent
7b1b2c5d87
commit
a35bba39bc
@ -3,7 +3,6 @@ require_relative "logic_helper"
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module Arm
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class CompareInstruction < Vm::CompareInstruction
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include Arm::Constants
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include LogicHelper
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def initialize(first , attributes)
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super(first , attributes)
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@ -14,8 +13,85 @@ module Arm
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@rn = first
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@rd = :r0
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end
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# arm intrucioons are pretty sensible, and always 4 bytes (thumb not supported)
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def length
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4
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end
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def build
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do_build @attributes[:right]
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arg = @attributes[:right]
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if arg.is_a?(Vm::StringConstant)
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# do pc relative addressing with the difference to the instuction
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# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
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arg = Vm::IntegerConstant.new( arg.position - self.position - 8 )
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@rn = :pc
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end
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if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
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arg = Vm::IntegerConstant.new( arg )
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end
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if (arg.is_a?(Vm::IntegerConstant))
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if (arg.integer.fits_u8?)
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# no shifting needed
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@operand = arg.integer
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@i = 1
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elsif (op_with_rot = calculate_u8_with_rr(arg))
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@operand = op_with_rot
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@i = 1
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raise "hmm"
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else
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raise "cannot fit numeric literal argument in operand #{arg.inspect}"
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end
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elsif (arg.is_a?(Symbol) or arg.is_a?(Vm::Integer))
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@operand = arg
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@i = 0
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elsif (arg.is_a?(Arm::Shift))
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rm_ref = arg.argument
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@i = 0
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shift_op = {'lsl' => 0b000, 'lsr' => 0b010, 'asr' => 0b100,
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'ror' => 0b110, 'rrx' => 0b110}[arg.type]
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if (arg.type == 'ror' and arg.value.nil?)
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# ror #0 == rrx
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raise "cannot rotate by zero #{arg} #{inspect}"
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end
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arg1 = arg.value
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if (arg1.is_a?(Vm::IntegerConstant))
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if (arg1.value >= 32)
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raise "cannot shift by more than 31 #{arg1} #{inspect}"
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end
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shift_imm = arg1.value
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elsif (arg1.is_a?(Arm::Register))
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shift_op val |= 0x1;
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shift_imm = arg1.number << 1
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elsif (arg.type == 'rrx')
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shift_imm = 0
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end
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@operand = rm_ref | (shift_op << 4) | (shift_imm << 4+3)
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else
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raise "invalid operand argument #{arg.inspect} , #{inspect}"
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end
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end
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def assemble(io)
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build
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instuction_class = 0b00 # OPC_DATA_PROCESSING
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val = (@operand.is_a?(Symbol) or @operand.is_a?(Vm::Integer)) ? reg_code(@operand) : @operand
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val = 0 if val == nil
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val = shift(val , 0)
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raise inspect unless reg_code(@rd)
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val |= shift(reg_code(@rd) , 12)
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val |= shift(reg_code(@rn) , 12+4)
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val |= shift(@attributes[:update_status] , 12+4+4)#20
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val |= shift(op_bit_code , 12+4+4 +1)
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val |= shift(@i , 12+4+4 +1+4)
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val |= shift(instuction_class , 12+4+4 +1+4+1)
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val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
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io.write_uint32 val
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end
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def shift val , by
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raise "Not integer #{val}:#{val.class}" unless val.is_a? Fixnum
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val << by
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end
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end
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end
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@ -1,98 +0,0 @@
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module Arm
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# Many arm instructions may be conditional, where the default condition is always (al)
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# Constants::COND_CODES names them, and this attribute reflects it
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#attr_reader :condition_code
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#attr_reader :operand
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# Logic instructions may be executed with or without affecting the status register
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# Only when an instruction affects the status is a subsequent compare instruction effective
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# But to make the conditional execution (see cond) work for more than one instruction, one needs to
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# be able to execute without changing the status
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#attr_reader :update_status
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module LogicHelper
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# ADDRESSING MODE 1
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# Logic ,Maths, Move and compare instructions (last three below)
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# arm intrucioons are pretty sensible, and always 4 bytes (thumb not supported)
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def length
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4
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end
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#(stays in subclases, while build is overriden to provide different arguments)
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def do_build(arg)
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if arg.is_a?(Vm::StringConstant)
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# do pc relative addressing with the difference to the instuction
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# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
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arg = Vm::IntegerConstant.new( arg.position - self.position - 8 )
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@rn = :pc
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end
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if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
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arg = Vm::IntegerConstant.new( arg )
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end
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if (arg.is_a?(Vm::IntegerConstant))
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if (arg.integer.fits_u8?)
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# no shifting needed
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@operand = arg.integer
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@i = 1
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elsif (op_with_rot = calculate_u8_with_rr(arg))
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@operand = op_with_rot
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@i = 1
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raise "hmm"
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else
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raise "cannot fit numeric literal argument in operand #{arg.inspect}"
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end
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elsif (arg.is_a?(Symbol) or arg.is_a?(Vm::Integer))
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@operand = arg
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@i = 0
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elsif (arg.is_a?(Arm::Shift))
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rm_ref = arg.argument
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@i = 0
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shift_op = {'lsl' => 0b000, 'lsr' => 0b010, 'asr' => 0b100,
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'ror' => 0b110, 'rrx' => 0b110}[arg.type]
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if (arg.type == 'ror' and arg.value.nil?)
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# ror #0 == rrx
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raise "cannot rotate by zero #{arg} #{inspect}"
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end
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arg1 = arg.value
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if (arg1.is_a?(Vm::IntegerConstant))
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if (arg1.value >= 32)
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raise "cannot shift by more than 31 #{arg1} #{inspect}"
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end
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shift_imm = arg1.value
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elsif (arg1.is_a?(Arm::Register))
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shift_op val |= 0x1;
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shift_imm = arg1.number << 1
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elsif (arg.type == 'rrx')
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shift_imm = 0
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end
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@operand = rm_ref | (shift_op << 4) | (shift_imm << 4+3)
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else
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raise "invalid operand argument #{arg.inspect} , #{inspect}"
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end
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end
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def assemble(io)
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build
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instuction_class = 0b00 # OPC_DATA_PROCESSING
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val = (@operand.is_a?(Symbol) or @operand.is_a?(Vm::Integer)) ? reg_code(@operand) : @operand
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val = 0 if val == nil
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val = shift(val , 0)
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raise inspect unless reg_code(@rd)
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val |= shift(reg_code(@rd) , 12)
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val |= shift(reg_code(@rn) , 12+4)
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val |= shift(@attributes[:update_status] , 12+4+4)#20
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val |= shift(op_bit_code , 12+4+4 +1)
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val |= shift(@i , 12+4+4 +1+4)
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val |= shift(instuction_class , 12+4+4 +1+4+1)
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val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
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io.write_uint32 val
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end
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def shift val , by
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raise "Not integer #{val}:#{val.class}" unless val.is_a? Fixnum
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val << by
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end
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end
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end
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