phase 1- get rid of the pesty args in structions

This commit is contained in:
Torsten Ruger 2014-05-10 15:47:27 +03:00
parent 3f88fe15b4
commit 8faf0ba17f
8 changed files with 20 additions and 25 deletions

View File

@ -59,7 +59,7 @@ module Arm
end end
def function_entry f_name def function_entry f_name
entry = Vm::Block.new("#{f_name}_entry") entry = Vm::Block.new("#{f_name}_entry")
# entry.add_code push( :left => :lr ) # entry.add_code push( :regs => [:lr] )
end end
def function_exit f_name def function_exit f_name
entry = Vm::Block.new("#{f_name}_exit") entry = Vm::Block.new("#{f_name}_exit")

View File

@ -27,14 +27,13 @@ module Arm
@update_status_flag = 0 @update_status_flag = 0
@condition_code = :al @condition_code = :al
@opcode = attributes[:opcode] @opcode = attributes[:opcode]
@args = [attributes[:left] , attributes[:right] , attributes[:extra]]
@operand = 0 @operand = 0
end end
def assemble(io) def assemble(io)
case @opcode case @opcode
when :b, :bl when :b, :bl
arg = @args[0] arg = @attributes[:left]
#puts "BLAB #{arg.inspect}" #puts "BLAB #{arg.inspect}"
if( arg.is_a? Fixnum ) #HACK to not have to change the code just now if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
arg = Arm::NumLiteral.new( arg ) arg = Arm::NumLiteral.new( arg )
@ -54,7 +53,7 @@ module Arm
end end
io.write_uint8 OPCODES[opcode] | (COND_CODES[@condition_code] << 4) io.write_uint8 OPCODES[opcode] | (COND_CODES[@condition_code] << 4)
when :swi when :swi
arg = @args[0] arg = @attributes[:left]
if( arg.is_a? Fixnum ) #HACK to not have to change the code just now if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
arg = Arm::NumLiteral.new( arg ) arg = Arm::NumLiteral.new( arg )
end end

View File

@ -10,15 +10,14 @@ module Arm
super(attributes) super(attributes)
@condition_code = :al @condition_code = :al
@opcode = attributes[:opcode] @opcode = attributes[:opcode]
@args = [attributes[:left] , attributes[:right] , attributes[:extra]]
@operand = 0 @operand = 0
@i = 0 @i = 0
@update_status_flag = 1 @update_status_flag = 1
@rn = @args[0] @rn = attributes[:left]
@rd = :r0 @rd = :r0
end end
def build def build
do_build @args[1] do_build @attributes[:right]
end end
end end
end end

View File

@ -12,18 +12,17 @@ module Arm
@update_status_flag = 0 @update_status_flag = 0
@condition_code = :al @condition_code = :al
@opcode = attributes[:opcode] @opcode = attributes[:opcode]
@args = [attributes[:left] , attributes[:right] , attributes[:extra]]
@operand = 0 @operand = 0
@rn = nil @rn = nil
@i = 0 @i = 0
@rd = @args[0] @rd = @attributes[:left]
end end
attr_accessor :i, :rn, :rd attr_accessor :i, :rn, :rd
# Build representation for source value # Build representation for source value
def build def build
@rn = @args[1] @rn = @attributes[:right]
do_build @args[2] do_build @attributes[:extra]
end end
end end
end end

View File

@ -12,7 +12,6 @@ module Arm
@update_status_flag = 0 @update_status_flag = 0
@condition_code = :al @condition_code = :al
@opcode = attributes[:opcode] @opcode = attributes[:opcode]
@args = [attributes[:left] , attributes[:right] ]
@operand = 0 @operand = 0
@i = 0 #I flag (third bit) @i = 0 #I flag (third bit)
@ -35,11 +34,11 @@ module Arm
# Build representation for target address # Build representation for target address
def build def build
if( @is_load ) if( @is_load )
@rd = @args[0] @rd = @attributes[:left]
arg = @args[1] arg = @attributes[:right]
else #store else #store
@rd = @args[1] @rd = @attributes[:right]
arg = @args[0] arg = @attributes[:left]
end end
#str / ldr are _serious instructions. With BIG possibilities not half are implemented #str / ldr are _serious instructions. With BIG possibilities not half are implemented
if (arg.is_a?(Symbol)) #symbol is register if (arg.is_a?(Symbol)) #symbol is register

View File

@ -12,16 +12,15 @@ module Arm
@update_status_flag = 0 @update_status_flag = 0
@condition_code = :al @condition_code = :al
@opcode = attributes[:opcode] @opcode = attributes[:opcode]
@args = [attributes[:left] , attributes[:right] , attributes[:extra]]
@operand = 0 @operand = 0
@i = 0 @i = 0
@rd = @args[0] @rd = @attributes[:left]
@rn = :r0 # register zero = zero bit pattern @rn = :r0 # register zero = zero bit pattern
end end
def build def build
do_build @args[1] do_build @attributes[:right]
end end
end end
end end

View File

@ -15,7 +15,6 @@ module Arm
@update_status_flag = 0 @update_status_flag = 0
@condition_code = :al @condition_code = :al
@opcode = attributes[:opcode] @opcode = attributes[:opcode]
@args = [attributes[:left] , attributes[:right] , attributes[:extra]]
@operand = 0 @operand = 0
@update_status_flag= 0 @update_status_flag= 0
@ -57,14 +56,15 @@ module Arm
private private
# Build representation for source value # Build representation for source value
def build def build
if (@args.is_a?(Array)) regs = @attributes[:regs]
if (regs.is_a?(Array))
@operand = 0 @operand = 0
@args.each do |reg | regs.each do |reg |
next unless reg next unless reg
@operand |= (1 << reg_code(reg)) @operand |= (1 << reg_code(reg))
end end
else else
raise "invalid operand argument #{@args.inspect} #{inspect}" raise "invalid operand argument #{regs.inspect} #{inspect}"
end end
end end
end end

View File

@ -82,11 +82,11 @@ class TestArmAsm < MiniTest::Test
assert_code code , :orr , [0x03,0x20,0x82,0xe1] #e1 82 20 03 assert_code code , :orr , [0x03,0x20,0x82,0xe1] #e1 82 20 03
end end
def test_push def test_push
code = @machine.push :left => :lr code = @machine.push :regs => [:lr]
assert_code code , :push , [0x00,0x40,0x2d,0xe9] #e9 2d 40 00 assert_code code , :push , [0x00,0x40,0x2d,0xe9] #e9 2d 40 00
end end
def test_pop def test_pop
code = @machine.pop :left => :pc code = @machine.pop :regs => [:pc]
assert_code code , :pop , [0x00,0x80,0xbd,0xe8] #e8 bd 80 00 assert_code code , :pop , [0x00,0x80,0xbd,0xe8] #e8 bd 80 00
end end
def test_rsb def test_rsb