diff --git a/lib/arm/arm_machine.rb b/lib/arm/arm_machine.rb index 0f2e5e8d..23fa6830 100644 --- a/lib/arm/arm_machine.rb +++ b/lib/arm/arm_machine.rb @@ -59,7 +59,7 @@ module Arm end def function_entry f_name entry = Vm::Block.new("#{f_name}_entry") -# entry.add_code push( :left => :lr ) +# entry.add_code push( :regs => [:lr] ) end def function_exit f_name entry = Vm::Block.new("#{f_name}_exit") diff --git a/lib/arm/call_instruction.rb b/lib/arm/call_instruction.rb index 003eb084..408df215 100644 --- a/lib/arm/call_instruction.rb +++ b/lib/arm/call_instruction.rb @@ -27,14 +27,13 @@ module Arm @update_status_flag = 0 @condition_code = :al @opcode = attributes[:opcode] - @args = [attributes[:left] , attributes[:right] , attributes[:extra]] @operand = 0 end def assemble(io) case @opcode when :b, :bl - arg = @args[0] + arg = @attributes[:left] #puts "BLAB #{arg.inspect}" if( arg.is_a? Fixnum ) #HACK to not have to change the code just now arg = Arm::NumLiteral.new( arg ) @@ -54,7 +53,7 @@ module Arm end io.write_uint8 OPCODES[opcode] | (COND_CODES[@condition_code] << 4) when :swi - arg = @args[0] + arg = @attributes[:left] if( arg.is_a? Fixnum ) #HACK to not have to change the code just now arg = Arm::NumLiteral.new( arg ) end diff --git a/lib/arm/compare_instruction.rb b/lib/arm/compare_instruction.rb index 2111601a..c17297e3 100644 --- a/lib/arm/compare_instruction.rb +++ b/lib/arm/compare_instruction.rb @@ -10,15 +10,14 @@ module Arm super(attributes) @condition_code = :al @opcode = attributes[:opcode] - @args = [attributes[:left] , attributes[:right] , attributes[:extra]] @operand = 0 @i = 0 @update_status_flag = 1 - @rn = @args[0] + @rn = attributes[:left] @rd = :r0 end def build - do_build @args[1] + do_build @attributes[:right] end end end \ No newline at end of file diff --git a/lib/arm/logic_instruction.rb b/lib/arm/logic_instruction.rb index bae86484..ecd48972 100644 --- a/lib/arm/logic_instruction.rb +++ b/lib/arm/logic_instruction.rb @@ -12,18 +12,17 @@ module Arm @update_status_flag = 0 @condition_code = :al @opcode = attributes[:opcode] - @args = [attributes[:left] , attributes[:right] , attributes[:extra]] @operand = 0 @rn = nil @i = 0 - @rd = @args[0] + @rd = @attributes[:left] end attr_accessor :i, :rn, :rd # Build representation for source value def build - @rn = @args[1] - do_build @args[2] + @rn = @attributes[:right] + do_build @attributes[:extra] end end end \ No newline at end of file diff --git a/lib/arm/memory_instruction.rb b/lib/arm/memory_instruction.rb index 0ddae894..db5f184f 100644 --- a/lib/arm/memory_instruction.rb +++ b/lib/arm/memory_instruction.rb @@ -12,7 +12,6 @@ module Arm @update_status_flag = 0 @condition_code = :al @opcode = attributes[:opcode] - @args = [attributes[:left] , attributes[:right] ] @operand = 0 @i = 0 #I flag (third bit) @@ -35,11 +34,11 @@ module Arm # Build representation for target address def build if( @is_load ) - @rd = @args[0] - arg = @args[1] + @rd = @attributes[:left] + arg = @attributes[:right] else #store - @rd = @args[1] - arg = @args[0] + @rd = @attributes[:right] + arg = @attributes[:left] end #str / ldr are _serious instructions. With BIG possibilities not half are implemented if (arg.is_a?(Symbol)) #symbol is register diff --git a/lib/arm/move_instruction.rb b/lib/arm/move_instruction.rb index e96c9ba4..80620740 100644 --- a/lib/arm/move_instruction.rb +++ b/lib/arm/move_instruction.rb @@ -12,16 +12,15 @@ module Arm @update_status_flag = 0 @condition_code = :al @opcode = attributes[:opcode] - @args = [attributes[:left] , attributes[:right] , attributes[:extra]] @operand = 0 @i = 0 - @rd = @args[0] + @rd = @attributes[:left] @rn = :r0 # register zero = zero bit pattern end def build - do_build @args[1] + do_build @attributes[:right] end end end \ No newline at end of file diff --git a/lib/arm/stack_instruction.rb b/lib/arm/stack_instruction.rb index 5fb01981..cb229d23 100644 --- a/lib/arm/stack_instruction.rb +++ b/lib/arm/stack_instruction.rb @@ -15,7 +15,6 @@ module Arm @update_status_flag = 0 @condition_code = :al @opcode = attributes[:opcode] - @args = [attributes[:left] , attributes[:right] , attributes[:extra]] @operand = 0 @update_status_flag= 0 @@ -57,14 +56,15 @@ module Arm private # Build representation for source value def build - if (@args.is_a?(Array)) + regs = @attributes[:regs] + if (regs.is_a?(Array)) @operand = 0 - @args.each do |reg | + regs.each do |reg | next unless reg @operand |= (1 << reg_code(reg)) end else - raise "invalid operand argument #{@args.inspect} #{inspect}" + raise "invalid operand argument #{regs.inspect} #{inspect}" end end end diff --git a/test/test_arm.rb b/test/test_arm.rb index 283ae3d3..8d170107 100644 --- a/test/test_arm.rb +++ b/test/test_arm.rb @@ -82,11 +82,11 @@ class TestArmAsm < MiniTest::Test assert_code code , :orr , [0x03,0x20,0x82,0xe1] #e1 82 20 03 end def test_push - code = @machine.push :left => :lr + code = @machine.push :regs => [:lr] assert_code code , :push , [0x00,0x40,0x2d,0xe9] #e9 2d 40 00 end def test_pop - code = @machine.pop :left => :pc + code = @machine.pop :regs => [:pc] assert_code code , :pop , [0x00,0x80,0xbd,0xe8] #e8 bd 80 00 end def test_rsb