phase 1- get rid of the pesty args in structions
This commit is contained in:
@ -59,7 +59,7 @@ module Arm
|
||||
end
|
||||
def function_entry f_name
|
||||
entry = Vm::Block.new("#{f_name}_entry")
|
||||
# entry.add_code push( :left => :lr )
|
||||
# entry.add_code push( :regs => [:lr] )
|
||||
end
|
||||
def function_exit f_name
|
||||
entry = Vm::Block.new("#{f_name}_exit")
|
||||
|
@ -27,14 +27,13 @@ module Arm
|
||||
@update_status_flag = 0
|
||||
@condition_code = :al
|
||||
@opcode = attributes[:opcode]
|
||||
@args = [attributes[:left] , attributes[:right] , attributes[:extra]]
|
||||
@operand = 0
|
||||
end
|
||||
|
||||
def assemble(io)
|
||||
case @opcode
|
||||
when :b, :bl
|
||||
arg = @args[0]
|
||||
arg = @attributes[:left]
|
||||
#puts "BLAB #{arg.inspect}"
|
||||
if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
|
||||
arg = Arm::NumLiteral.new( arg )
|
||||
@ -54,7 +53,7 @@ module Arm
|
||||
end
|
||||
io.write_uint8 OPCODES[opcode] | (COND_CODES[@condition_code] << 4)
|
||||
when :swi
|
||||
arg = @args[0]
|
||||
arg = @attributes[:left]
|
||||
if( arg.is_a? Fixnum ) #HACK to not have to change the code just now
|
||||
arg = Arm::NumLiteral.new( arg )
|
||||
end
|
||||
|
@ -10,15 +10,14 @@ module Arm
|
||||
super(attributes)
|
||||
@condition_code = :al
|
||||
@opcode = attributes[:opcode]
|
||||
@args = [attributes[:left] , attributes[:right] , attributes[:extra]]
|
||||
@operand = 0
|
||||
@i = 0
|
||||
@update_status_flag = 1
|
||||
@rn = @args[0]
|
||||
@rn = attributes[:left]
|
||||
@rd = :r0
|
||||
end
|
||||
def build
|
||||
do_build @args[1]
|
||||
do_build @attributes[:right]
|
||||
end
|
||||
end
|
||||
end
|
@ -12,18 +12,17 @@ module Arm
|
||||
@update_status_flag = 0
|
||||
@condition_code = :al
|
||||
@opcode = attributes[:opcode]
|
||||
@args = [attributes[:left] , attributes[:right] , attributes[:extra]]
|
||||
@operand = 0
|
||||
|
||||
@rn = nil
|
||||
@i = 0
|
||||
@rd = @args[0]
|
||||
@rd = @attributes[:left]
|
||||
end
|
||||
attr_accessor :i, :rn, :rd
|
||||
# Build representation for source value
|
||||
def build
|
||||
@rn = @args[1]
|
||||
do_build @args[2]
|
||||
@rn = @attributes[:right]
|
||||
do_build @attributes[:extra]
|
||||
end
|
||||
end
|
||||
end
|
@ -12,7 +12,6 @@ module Arm
|
||||
@update_status_flag = 0
|
||||
@condition_code = :al
|
||||
@opcode = attributes[:opcode]
|
||||
@args = [attributes[:left] , attributes[:right] ]
|
||||
@operand = 0
|
||||
|
||||
@i = 0 #I flag (third bit)
|
||||
@ -35,11 +34,11 @@ module Arm
|
||||
# Build representation for target address
|
||||
def build
|
||||
if( @is_load )
|
||||
@rd = @args[0]
|
||||
arg = @args[1]
|
||||
@rd = @attributes[:left]
|
||||
arg = @attributes[:right]
|
||||
else #store
|
||||
@rd = @args[1]
|
||||
arg = @args[0]
|
||||
@rd = @attributes[:right]
|
||||
arg = @attributes[:left]
|
||||
end
|
||||
#str / ldr are _serious instructions. With BIG possibilities not half are implemented
|
||||
if (arg.is_a?(Symbol)) #symbol is register
|
||||
|
@ -12,16 +12,15 @@ module Arm
|
||||
@update_status_flag = 0
|
||||
@condition_code = :al
|
||||
@opcode = attributes[:opcode]
|
||||
@args = [attributes[:left] , attributes[:right] , attributes[:extra]]
|
||||
@operand = 0
|
||||
|
||||
@i = 0
|
||||
@rd = @args[0]
|
||||
@rd = @attributes[:left]
|
||||
@rn = :r0 # register zero = zero bit pattern
|
||||
end
|
||||
|
||||
def build
|
||||
do_build @args[1]
|
||||
do_build @attributes[:right]
|
||||
end
|
||||
end
|
||||
end
|
@ -15,7 +15,6 @@ module Arm
|
||||
@update_status_flag = 0
|
||||
@condition_code = :al
|
||||
@opcode = attributes[:opcode]
|
||||
@args = [attributes[:left] , attributes[:right] , attributes[:extra]]
|
||||
@operand = 0
|
||||
|
||||
@update_status_flag= 0
|
||||
@ -57,14 +56,15 @@ module Arm
|
||||
private
|
||||
# Build representation for source value
|
||||
def build
|
||||
if (@args.is_a?(Array))
|
||||
regs = @attributes[:regs]
|
||||
if (regs.is_a?(Array))
|
||||
@operand = 0
|
||||
@args.each do |reg |
|
||||
regs.each do |reg |
|
||||
next unless reg
|
||||
@operand |= (1 << reg_code(reg))
|
||||
end
|
||||
else
|
||||
raise "invalid operand argument #{@args.inspect} #{inspect}"
|
||||
raise "invalid operand argument #{regs.inspect} #{inspect}"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
Reference in New Issue
Block a user