cleaned intruction initialization and fixed a test accidentally (was schoddy code)
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@ -23,8 +23,7 @@ module Asm
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end
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attr_reader :codes , :position
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def instruction(clazz,name, *args)
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opcode = name.to_s
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def instruction(clazz, opcode , condition_code , update_status , *args)
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arg_nodes = []
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args.each do |arg|
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if (arg.is_a?(Asm::Register))
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@ -39,24 +38,23 @@ module Asm
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raise "Invalid argument #{arg.inspect} for instruction"
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end
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end
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add_code clazz.new(opcode , arg_nodes)
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add_code clazz.new(opcode , condition_code , update_status , arg_nodes)
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end
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def self.define_instruction(inst , clazz )
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define_method(inst) do |*args|
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instruction clazz , inst , *args
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instruction clazz , inst , :al , 0 , *args
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end
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define_method(inst.to_s+'s') do |*args|
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instruction clazz , inst.to_s+'s' , *args
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define_method("#{inst}s") do |*args|
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instruction clazz , inst , :al , 1 , *args
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end
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ArmMachine::COND_CODES.keys.each do |cond_suffix|
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suffix = cond_suffix.to_s
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define_method(inst.to_s + suffix) do |*args|
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instruction clazz , inst + suffix , *args
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ArmMachine::COND_CODES.keys.each do |suffix|
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define_method("#{inst}#{suffix}") do |*args|
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instruction clazz , inst , suffix , 0 , *args
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end
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define_method(inst.to_s + 's'+ suffix) do |*args|
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instruction clazz , inst.to_s + 's' + suffix, *args
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define_method("#{inst}s#{suffix}") do |*args|
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instruction clazz , inst , suffix , 1 , *args
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end
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end
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end
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@ -39,9 +39,9 @@ module Asm
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:ge => 0b1010, :gt => 0b1100,
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:vs => 0b0110
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}
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#return the bit pattern for the @cond variable, which signals the conditional code
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#return the bit pattern for the @condition_code variable, which signals the conditional code
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def cond_bit_code
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COND_CODES[@cond] or throw "no code found for #{@cond}"
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COND_CODES[@condition_code] or throw "no code found for #{@condition_code}"
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end
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REGISTERS = { 'r0' => 0, 'r1' => 1, 'r2' => 2, 'r3' => 3, 'r4' => 4, 'r5' => 5,
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@ -12,10 +12,6 @@ module Asm
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# Registers 0-6 hold the call values as for a normal c call
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class CallInstruction < Instruction
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def initialize(opcode , args)
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super(opcode,args)
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end
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def assemble(io)
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case opcode
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@ -34,13 +30,13 @@ module Asm
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else
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raise "else not coded #{arg.inspect}"
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end
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io.write_uint8 OPCODES[opcode] | (COND_CODES[@cond] << 4)
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io.write_uint8 OPCODES[opcode] | (COND_CODES[@condition_code] << 4)
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when :swi
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arg = args[0]
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if (arg.is_a?(Asm::NumLiteral))
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packed = [arg.value].pack('L')[0,3]
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io << packed
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io.write_uint8 0b1111 | (COND_CODES[@cond] << 4)
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io.write_uint8 0b1111 | (COND_CODES[@condition_code] << 4)
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else
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raise Asm::AssemblyError.new("invalid operand argument expected literal not #{arg}")
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end
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@ -17,20 +17,10 @@ module Asm
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COND_POSTFIXES = Regexp.union( COND_CODES.keys.collect{|k|k.to_s} ).source
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def initialize(opcode , args)
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opcode = opcode.to_s.downcase
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@cond = :al
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if (opcode =~ /(#{COND_POSTFIXES})$/)
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@cond = $1.to_sym
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opcode = opcode[0..-3]
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end unless opcode == 'teq'
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if (opcode =~ /s$/)
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@update_status_flag= 1
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opcode = opcode[0..-2]
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else
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@update_status_flag= 0
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end
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@opcode = opcode.downcase.to_sym
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def initialize(opcode , condition_code , update_status , args)
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@update_status_flag = update_status
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@condition_code = condition_code.to_sym
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@opcode = opcode
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@args = args
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@operand = 0
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end
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@ -38,7 +28,7 @@ module Asm
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attr_reader :opcode, :args
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# Many arm instructions may be conditional, where the default condition is always (al)
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# ArmMachine::COND_CODES names them, and this attribute reflects it
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attr_reader :cond
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attr_reader :condition_code
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attr_reader :operand
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# Logic instructions may be executed with or without affecting the status register
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@ -4,10 +4,10 @@ module Asm
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class LogicInstruction < Instruction
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def initialize( opcode , args)
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super(opcode , args)
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def initialize(opcode , condition_code , update_status , args)
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super(opcode , condition_code , update_status , args)
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@rn = nil
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@i = 0
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@i = 0
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@rd = args[0]
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end
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attr_accessor :i, :rn, :rd
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@ -19,7 +19,7 @@ module Asm
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end
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#(stays in subclases, while build is overriden to provide different arguments)
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def do_build(arg)
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def do_build(arg)
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if arg.is_a?(Asm::StringLiteral)
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# do pc relative addressing with the difference to the instuction
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# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
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@ -72,8 +72,8 @@ module Asm
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build
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instuction_class = 0b00 # OPC_DATA_PROCESSING
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val = operand.is_a?(Register) ? operand.bits : operand
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val |= (rd.bits << 12)
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val |= (rn.bits << 12+4)
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val |= (rd.bits << 12)
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val |= (rn.bits << 12+4)
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val |= (update_status_flag << 12+4+4)#20
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val |= (op_bit_code << 12+4+4 +1)
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val |= (i << 12+4+4 +1+4)
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@ -83,8 +83,8 @@ module Asm
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end
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end
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class CompareInstruction < LogicInstruction
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def initialize( opcode , args)
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super(opcode , args)
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def initialize(opcode , condition_code , update_status , args)
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super(opcode , condition_code , update_status , args)
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@update_status_flag = 1
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@rn = args[0]
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@rd = reg "r0"
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@ -94,8 +94,8 @@ module Asm
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end
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end
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class MoveInstruction < LogicInstruction
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def initialize( opcode , args)
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super(opcode , args)
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def initialize(opcode , condition_code , update_status , args)
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super(opcode , condition_code , update_status , args)
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@rn = reg "r0" # register zero = zero bit pattern
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end
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def build
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@ -5,8 +5,8 @@ module Asm
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# Implemented: immediate offset with offset=0
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class MemoryInstruction < Instruction
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def initialize(opcode , args)
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super( opcode , args )
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def initialize(opcode , condition_code , update_status , args)
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super(opcode , condition_code , update_status , args)
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@i = 0 #I flag (third bit)
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@pre_post_index = 0 #P flag
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@add_offset = 0 #U flag
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@ -4,8 +4,8 @@ module Asm
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# ADDRESSING MODE 4
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class StackInstruction < Instruction
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def initialize(opcode , args)
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super(opcode,args)
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def initialize(opcode , condition_code , update_status , args)
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super(opcode , condition_code , update_status , args)
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@update_status_flag= 0
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@rn = reg "r0" # register zero = zero bit pattern
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# downward growing, decrement before memory access
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@ -27,7 +27,7 @@ module Asm
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def assemble(io)
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build
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instuction_class = 0b10 # OPC_STACK
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cond = @cond.is_a?(Symbol) ? COND_CODES[@cond] : @cond
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cond = @condition_code.is_a?(Symbol) ? COND_CODES[@condition_code] : @condition_code
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rn = reg "sp" # sp register
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#assemble of old
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val = operand
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