removing unconditional

just Branch is fine
This commit is contained in:
Torsten Ruger 2018-04-02 19:30:34 +03:00
parent 299a130761
commit 65d57c8c7c
4 changed files with 6 additions and 10 deletions

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@ -1,9 +1,9 @@
module Mom module Mom
# Unconditional jump to the Label given # Branch jump to the Label given
# Eg used at the end of while or end of if_true branch # Eg used at the end of while or end of if_true branch
# #
# Risc equivalent is the same really, called Unconditional there. # Risc equivalent is the same really, called Branch there.
# #
class Jump < Instruction class Jump < Instruction
attr_reader :label attr_reader :label
@ -12,7 +12,7 @@ module Mom
@label = label @label = label
end end
def to_risc(compiler) def to_risc(compiler)
Risc::Unconditional.new(self , @label.to_risc(compiler)) Risc::Branch.new(self , @label.to_risc(compiler))
end end
end end

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@ -17,7 +17,7 @@ module Risc
end end
# dynamic version of an Unconditional branch that jumps to the contents # dynamic version of an Branch branch that jumps to the contents
# of a register instead of a hardcoded address # of a register instead of a hardcoded address
# As Branches jump to Labels, this is not derived from Branch # As Branches jump to Labels, this is not derived from Branch
# PS: to conditionally jump to a dynamic adddress we do a normal branch # PS: to conditionally jump to a dynamic adddress we do a normal branch
@ -31,10 +31,6 @@ module Risc
attr_reader :register attr_reader :register
end end
class Unconditional < Branch
end
class IsZero < Branch class IsZero < Branch
end end

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@ -9,7 +9,7 @@ module Risc
@input = "if(@a) ; arg = 5 ; else; arg = 6; end" @input = "if(@a) ; arg = 5 ; else; arg = 6; end"
@expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsNotZero , @expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsNotZero ,
LoadConstant, OperatorInstruction, IsNotZero, Label, LoadConstant , LoadConstant, OperatorInstruction, IsNotZero, Label, LoadConstant ,
SlotToReg, RegToSlot, Unconditional, Label, LoadConstant , SlotToReg, RegToSlot, Branch, Label, LoadConstant ,
SlotToReg, RegToSlot, Label] SlotToReg, RegToSlot, Label]
end end

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@ -9,7 +9,7 @@ module Risc
@input = "while(@a) ; arg = 5 end" @input = "while(@a) ; arg = 5 end"
@expect = [Label, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction , @expect = [Label, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction ,
IsNotZero, LoadConstant, OperatorInstruction, IsNotZero, LoadConstant , IsNotZero, LoadConstant, OperatorInstruction, IsNotZero, LoadConstant ,
SlotToReg, RegToSlot, Unconditional, Label] SlotToReg, RegToSlot, Branch, Label]
end end
def test_while_instructions def test_while_instructions