removing unconditional
just Branch is fine
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parent
299a130761
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@ -1,9 +1,9 @@
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module Mom
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module Mom
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# Unconditional jump to the Label given
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# Branch jump to the Label given
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# Eg used at the end of while or end of if_true branch
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# Eg used at the end of while or end of if_true branch
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#
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#
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# Risc equivalent is the same really, called Unconditional there.
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# Risc equivalent is the same really, called Branch there.
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#
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#
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class Jump < Instruction
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class Jump < Instruction
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attr_reader :label
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attr_reader :label
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@ -12,7 +12,7 @@ module Mom
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@label = label
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@label = label
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end
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end
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def to_risc(compiler)
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def to_risc(compiler)
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Risc::Unconditional.new(self , @label.to_risc(compiler))
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Risc::Branch.new(self , @label.to_risc(compiler))
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end
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end
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end
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end
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@ -17,7 +17,7 @@ module Risc
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end
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end
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# dynamic version of an Unconditional branch that jumps to the contents
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# dynamic version of an Branch branch that jumps to the contents
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# of a register instead of a hardcoded address
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# of a register instead of a hardcoded address
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# As Branches jump to Labels, this is not derived from Branch
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# As Branches jump to Labels, this is not derived from Branch
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# PS: to conditionally jump to a dynamic adddress we do a normal branch
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# PS: to conditionally jump to a dynamic adddress we do a normal branch
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@ -31,10 +31,6 @@ module Risc
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attr_reader :register
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attr_reader :register
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end
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end
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class Unconditional < Branch
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end
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class IsZero < Branch
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class IsZero < Branch
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end
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end
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@ -9,7 +9,7 @@ module Risc
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@input = "if(@a) ; arg = 5 ; else; arg = 6; end"
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@input = "if(@a) ; arg = 5 ; else; arg = 6; end"
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@expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsNotZero ,
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@expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsNotZero ,
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LoadConstant, OperatorInstruction, IsNotZero, Label, LoadConstant ,
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LoadConstant, OperatorInstruction, IsNotZero, Label, LoadConstant ,
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SlotToReg, RegToSlot, Unconditional, Label, LoadConstant ,
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SlotToReg, RegToSlot, Branch, Label, LoadConstant ,
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SlotToReg, RegToSlot, Label]
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SlotToReg, RegToSlot, Label]
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end
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end
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@ -9,7 +9,7 @@ module Risc
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@input = "while(@a) ; arg = 5 end"
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@input = "while(@a) ; arg = 5 end"
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@expect = [Label, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction ,
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@expect = [Label, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction ,
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IsNotZero, LoadConstant, OperatorInstruction, IsNotZero, LoadConstant ,
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IsNotZero, LoadConstant, OperatorInstruction, IsNotZero, LoadConstant ,
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SlotToReg, RegToSlot, Unconditional, Label]
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SlotToReg, RegToSlot, Branch, Label]
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end
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end
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def test_while_instructions
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def test_while_instructions
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