From 65d57c8c7c66966ddfcf9d28d8200696608bdb09 Mon Sep 17 00:00:00 2001 From: Torsten Ruger Date: Mon, 2 Apr 2018 19:30:34 +0300 Subject: [PATCH] removing unconditional just Branch is fine --- lib/mom/instruction/jump.rb | 6 +++--- lib/risc/instructions/branch.rb | 6 +----- test/mom/test_if_else.rb | 2 +- test/mom/test_while.rb | 2 +- 4 files changed, 6 insertions(+), 10 deletions(-) diff --git a/lib/mom/instruction/jump.rb b/lib/mom/instruction/jump.rb index 9bdb3cb1..8ec76f61 100644 --- a/lib/mom/instruction/jump.rb +++ b/lib/mom/instruction/jump.rb @@ -1,9 +1,9 @@ module Mom - # Unconditional jump to the Label given + # Branch jump to the Label given # Eg used at the end of while or end of if_true branch # - # Risc equivalent is the same really, called Unconditional there. + # Risc equivalent is the same really, called Branch there. # class Jump < Instruction attr_reader :label @@ -12,7 +12,7 @@ module Mom @label = label end def to_risc(compiler) - Risc::Unconditional.new(self , @label.to_risc(compiler)) + Risc::Branch.new(self , @label.to_risc(compiler)) end end diff --git a/lib/risc/instructions/branch.rb b/lib/risc/instructions/branch.rb index 38e96f79..42190bb4 100644 --- a/lib/risc/instructions/branch.rb +++ b/lib/risc/instructions/branch.rb @@ -17,7 +17,7 @@ module Risc end - # dynamic version of an Unconditional branch that jumps to the contents + # dynamic version of an Branch branch that jumps to the contents # of a register instead of a hardcoded address # As Branches jump to Labels, this is not derived from Branch # PS: to conditionally jump to a dynamic adddress we do a normal branch @@ -31,10 +31,6 @@ module Risc attr_reader :register end - class Unconditional < Branch - - end - class IsZero < Branch end diff --git a/test/mom/test_if_else.rb b/test/mom/test_if_else.rb index 856a067e..f22247a2 100644 --- a/test/mom/test_if_else.rb +++ b/test/mom/test_if_else.rb @@ -9,7 +9,7 @@ module Risc @input = "if(@a) ; arg = 5 ; else; arg = 6; end" @expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsNotZero , LoadConstant, OperatorInstruction, IsNotZero, Label, LoadConstant , - SlotToReg, RegToSlot, Unconditional, Label, LoadConstant , + SlotToReg, RegToSlot, Branch, Label, LoadConstant , SlotToReg, RegToSlot, Label] end diff --git a/test/mom/test_while.rb b/test/mom/test_while.rb index ca6515f2..14b8c91f 100644 --- a/test/mom/test_while.rb +++ b/test/mom/test_while.rb @@ -9,7 +9,7 @@ module Risc @input = "while(@a) ; arg = 5 end" @expect = [Label, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction , IsNotZero, LoadConstant, OperatorInstruction, IsNotZero, LoadConstant , - SlotToReg, RegToSlot, Unconditional, Label] + SlotToReg, RegToSlot, Branch, Label] end def test_while_instructions