removing unconditional
just Branch is fine
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@ -9,7 +9,7 @@ module Risc
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@input = "if(@a) ; arg = 5 ; else; arg = 6; end"
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@expect = [SlotToReg, SlotToReg, LoadConstant, OperatorInstruction, IsNotZero ,
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LoadConstant, OperatorInstruction, IsNotZero, Label, LoadConstant ,
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SlotToReg, RegToSlot, Unconditional, Label, LoadConstant ,
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SlotToReg, RegToSlot, Branch, Label, LoadConstant ,
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SlotToReg, RegToSlot, Label]
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end
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@ -9,7 +9,7 @@ module Risc
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@input = "while(@a) ; arg = 5 end"
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@expect = [Label, SlotToReg, SlotToReg, LoadConstant, OperatorInstruction ,
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IsNotZero, LoadConstant, OperatorInstruction, IsNotZero, LoadConstant ,
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SlotToReg, RegToSlot, Unconditional, Label]
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SlotToReg, RegToSlot, Branch, Label]
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end
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def test_while_instructions
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