fix slot_to_reg to allow register indexes
we mostly use pre-calculated indexes, ie integers but registers are allowed (in arm/risc), so we try to check the registers type at least is right. The return is really a machine word, but we call it Object (yes, more work that way)
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@ -23,15 +23,9 @@ module Risc
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# fullfil the objects purpose by creating a RegToSlot instruction from
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# itself (the slot) and the register given
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def <<( reg )
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case reg
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when RegisterValue
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to_mem("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg)
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when RegisterSlot
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reg = to_reg()
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to_mem("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg)
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else
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raise "not reg value or slot #{reg}"
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end
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reg = reg.to_reg() if reg.is_a?( RegisterSlot )
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raise "not reg value or slot #{reg}" unless reg.is_a?(RegisterValue)
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to_mem("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg)
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end
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# for chaining the array operator is defined here too.
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@ -59,7 +53,7 @@ module Risc
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# the register is created, and the slot_to_reg instruction added to the
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# compiler. the return is a bit like @register[@index]
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def to_reg()
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source = "reduce #{@register.symbol}[@index]"
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source = "reduce #{@register.symbol}[#{@index}]"
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slot_to_reg = Risc.slot_to_reg(source , register, index)
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if compiler
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compiler.add_code(slot_to_reg)
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