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finish the loop in slot_load

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thus rewrite of that old nested if thing is done
This commit is contained in:
Torsten Ruger 2018-07-14 11:04:21 +03:00
parent 581f457119
commit 58c7294abd
2 changed files with 7 additions and 29 deletions
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30
lib/mom/instruction/slot_load.rb
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@ -62,36 +62,14 @@ module Mom
raise "Not Message #{object}" unless @left.known_object == :message raise "Not Message #{object}" unless @left.known_object == :message
left = Risc.message_reg left = Risc.message_reg
slot = left_slots.shift slot = left_slots.shift
while( !left_slots.empty? )
left = left.resolve_and_add( slot , const , compiler) left = left.resolve_and_add( slot , const , compiler)
slot = left_slots.shift
#left_index = Risc.resolve_to_index(@left.known_object , left_slots.first) end
left_index = left.resolve_index( slot )
const << Risc.reg_to_slot(original_source, const.register , left, left_index) const << Risc.reg_to_slot(original_source, const.register , left, left_index)
end end
def old_sym_to_risc(compiler , const)
left = Risc.message_reg
left_slots = @left.slots
left_index = Risc.resolve_to_index(@left.known_object , left_slots.first)
if left_slots.length > 1
# swap the existing target (with a new reg) and update the index
new_left = compiler.use_reg( :Object )
const << Risc::SlotToReg.new( original_source , left ,left_index, new_left)
left = new_left
left_index = Risc.resolve_to_index(left_slots[0] , left_slots[1] ,compiler)
if left_slots.length > 2
#same again, once more updating target
new_left = compiler.use_reg( :Object )
const << Risc::SlotToReg.new( original_source , left ,left_index, new_left)
left = new_left
left_index = Risc.resolve_to_index(left_slots[1] , left_slots[2] ,compiler)
end
raise "more slots not implemented #{left_slots}" if left_slots.length > 3
end
const << Risc.reg_to_slot(original_source, const.register , left, left_index)
end
end end
end end

6
lib/risc/register_value.rb
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@ -20,7 +20,7 @@ module Risc
def resolve_and_add(slot , instruction , compiler) def resolve_and_add(slot , instruction , compiler)
index = resolve_index( slot ) index = resolve_index( slot )
new_left = get_new_left( slot , compiler ) new_left = get_new_left( slot , compiler )
instruction << Risc::SlotToReg.new( "SlotLoad #{type}[#{slot}]" , @symbol ,index, new_left) instruction << Risc::SlotToReg.new( "SlotLoad #{type}[#{slot}]" , self ,index, new_left)
new_left new_left
end end
@ -43,9 +43,9 @@ module Risc
def get_new_left(slot, compiler) def get_new_left(slot, compiler)
new_type = resolve_new_type(slot , compiler) new_type = resolve_new_type(slot , compiler)
if( @symbol == :r0 ) if( @symbol == :r0 )
new_left = compiler.use_reg( new_type ) new_left = compiler.use_reg( new_type.class_name )
else else
new_left = RegisterValue.new( @symbol , new_type) new_left = RegisterValue.new( @symbol , new_type.class_name)
end end
new_left new_left
end end