From 58c7294abd2617aa72dba8fb1be8a16f87fe713b Mon Sep 17 00:00:00 2001
From: Torsten Ruger <torsten@villataika.fi>
Date: Sat, 14 Jul 2018 11:04:21 +0300
Subject: [PATCH] finish the loop in slot_load

thus rewrite of that old nested if thing is done
---
 lib/mom/instruction/slot_load.rb | 30 ++++--------------------------
 lib/risc/register_value.rb       |  6 +++---
 2 files changed, 7 insertions(+), 29 deletions(-)

diff --git a/lib/mom/instruction/slot_load.rb b/lib/mom/instruction/slot_load.rb
index ca54b875..2fb64aa3 100644
--- a/lib/mom/instruction/slot_load.rb
+++ b/lib/mom/instruction/slot_load.rb
@@ -62,36 +62,14 @@ module Mom
       raise "Not Message #{object}" unless @left.known_object == :message
       left = Risc.message_reg
       slot = left_slots.shift
-      left = left.resolve_and_add( slot , const , compiler)
-
-      #left_index = Risc.resolve_to_index(@left.known_object , left_slots.first)
-
-      const << Risc.reg_to_slot(original_source, const.register , left, left_index)
-    end
-
-    def old_sym_to_risc(compiler , const)
-      left = Risc.message_reg
-      left_slots = @left.slots
-      left_index = Risc.resolve_to_index(@left.known_object , left_slots.first)
-      if left_slots.length > 1
-        # swap the existing target (with a new reg) and update the index
-        new_left = compiler.use_reg( :Object )
-        const << Risc::SlotToReg.new( original_source , left ,left_index, new_left)
-        left = new_left
-        left_index = Risc.resolve_to_index(left_slots[0] , left_slots[1] ,compiler)
-        if left_slots.length > 2
-          #same again, once more updating target
-          new_left = compiler.use_reg( :Object )
-          const << Risc::SlotToReg.new( original_source , left ,left_index, new_left)
-          left = new_left
-          left_index = Risc.resolve_to_index(left_slots[1] , left_slots[2] ,compiler)
-        end
-        raise "more slots not implemented #{left_slots}" if left_slots.length > 3
+      while( !left_slots.empty? )
+        left = left.resolve_and_add( slot , const , compiler)
+        slot = left_slots.shift
       end
+      left_index = left.resolve_index( slot )
       const << Risc.reg_to_slot(original_source, const.register , left, left_index)
     end
 
-
   end
 
 end
diff --git a/lib/risc/register_value.rb b/lib/risc/register_value.rb
index 7ccbbf5b..63300f53 100644
--- a/lib/risc/register_value.rb
+++ b/lib/risc/register_value.rb
@@ -20,7 +20,7 @@ module Risc
     def resolve_and_add(slot , instruction , compiler)
       index = resolve_index( slot )
       new_left = get_new_left( slot , compiler )
-      instruction << Risc::SlotToReg.new( "SlotLoad #{type}[#{slot}]" , @symbol ,index, new_left)
+      instruction << Risc::SlotToReg.new( "SlotLoad #{type}[#{slot}]" , self ,index, new_left)
       new_left
     end
 
@@ -43,9 +43,9 @@ module Risc
     def get_new_left(slot, compiler)
       new_type = resolve_new_type(slot , compiler)
       if( @symbol == :r0 )
-        new_left = compiler.use_reg( new_type )
+        new_left = compiler.use_reg( new_type.class_name )
       else
-        new_left = RegisterValue.new( @symbol , new_type)
+        new_left = RegisterValue.new( @symbol , new_type.class_name)
       end
       new_left
     end