finish the loop in slot_load
thus rewrite of that old nested if thing is done
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@ -20,7 +20,7 @@ module Risc
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def resolve_and_add(slot , instruction , compiler)
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index = resolve_index( slot )
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new_left = get_new_left( slot , compiler )
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instruction << Risc::SlotToReg.new( "SlotLoad #{type}[#{slot}]" , @symbol ,index, new_left)
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instruction << Risc::SlotToReg.new( "SlotLoad #{type}[#{slot}]" , self ,index, new_left)
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new_left
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end
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@ -43,9 +43,9 @@ module Risc
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def get_new_left(slot, compiler)
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new_type = resolve_new_type(slot , compiler)
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if( @symbol == :r0 )
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new_left = compiler.use_reg( new_type )
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new_left = compiler.use_reg( new_type.class_name )
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else
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new_left = RegisterValue.new( @symbol , new_type)
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new_left = RegisterValue.new( @symbol , new_type.class_name)
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end
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new_left
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end
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