add source to instruction

for debug
This commit is contained in:
Torsten Ruger 2015-07-18 11:21:49 +03:00
parent 50da6a40f2
commit 53d8f4b163
5 changed files with 21 additions and 3 deletions

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@ -9,6 +9,11 @@ module Register
# constants can/must be loaded into registers before use # constants can/must be loaded into registers before use
class Instruction class Instruction
def initialize source
@source = source
end
attr_reader :block , :source
# returns an array of registers (RegisterReferences) that this instruction uses. # returns an array of registers (RegisterReferences) that this instruction uses.
# ie for r1 = r2 + r3 # ie for r1 = r2 + r3
# which in assembler is add r1 , r2 , r3 # which in assembler is add r1 , r2 , r3

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@ -3,10 +3,17 @@ module Register
# a branch must branch to a block. # a branch must branch to a block.
class Branch < Instruction class Branch < Instruction
def initialize to def initialize source , to
super(source)
raise "No block" unless to raise "No block" unless to
@block = to @block = to
end end
attr_reader :block attr_reader :block
def to_s
"Branch(to: #{block.name})"
end
end end
end end

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@ -8,7 +8,7 @@ module Register
def run block def run block
block.codes.dup.each do |code| block.codes.dup.each do |code|
next unless code.is_a? Virtual::VirtualMain next unless code.is_a? Virtual::VirtualMain
branch = Register::Branch.new( code.method.source.blocks.first ) branch = Register::Branch.new( code , code.method.source.blocks.first )
block.replace(code , branch ) block.replace(code , branch )
end end
end end

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@ -15,5 +15,9 @@ module Virtual
def word_length def word_length
4 4
end end
def to_s
"#{self.class.name}( method: #{method.name})"
end
end end
end end

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@ -35,6 +35,8 @@ module Virtual
class Machine class Machine
FIRST_PASS = "Virtual::SendImplementation" FIRST_PASS = "Virtual::SendImplementation"
LAST_PASS = "Virtual::SetOptimisation"
def initialize def initialize
@parser = Parser::Salama.new @parser = Parser::Salama.new
@passes = [ FIRST_PASS ] @passes = [ FIRST_PASS ]