test and last fixes for previous commits (allocalte ints)

mostly just fixing the additional instructions
close #20
This commit is contained in:
Torsten Ruger
2018-11-24 22:40:22 +02:00
parent e6615d0a6a
commit 4d30727811
19 changed files with 308 additions and 233 deletions

View File

@ -64,7 +64,9 @@ module Risc
str = all.collect{|i| i.class.name}.join(", ").gsub("Risc::","")
str = "[#{str}]"
all = str.split(",").each_slice(5).collect { |line| " " + line.join(",")}
all.join(",\n")
res = ""
all.each_with_index { |line,index| res += "#{line}, ##{index*5 + 4}\n"}
res
end
end
end

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@ -7,18 +7,18 @@ module Risc
def setup
super
@input = "@a.div4"
@expect = [LoadConstant, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg,
LoadConstant, RegToSlot, LoadConstant, LoadConstant, SlotToReg,
SlotToReg, Label, LoadConstant, OperatorInstruction, IsZero,
SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch,
Label, Transfer, Syscall, Transfer, Transfer,
LoadConstant, SlotToReg, SlotToReg, RegToSlot, RegToSlot,
RegToSlot, Label, RegToSlot, Label, LoadConstant,
SlotToReg, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
SlotToReg, LoadConstant, SlotToReg, DynamicJump, Label]
@expect = [LoadConstant, SlotToReg, SlotToReg, SlotToReg, SlotToReg, #4
OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg, #9
LoadConstant, RegToSlot, LoadConstant, LoadConstant, SlotToReg, #14
SlotToReg, Label, LoadConstant, OperatorInstruction, IsZero, #19
SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch, #24
Label, LoadConstant, SlotToReg, Transfer, Syscall, #29
Transfer, Transfer, SlotToReg, RegToSlot, Label, #34
RegToSlot, Label, LoadConstant, SlotToReg, LoadConstant, #39
SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot, #44
RegToSlot, SlotToReg, SlotToReg, SlotToReg, RegToSlot, #49
LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant, #54
SlotToReg, DynamicJump, Label]
end
def test_send_instructions
@ -26,23 +26,23 @@ module Risc
end
def test_sys
produced = produce_body
assert_equal Syscall , produced.next(27).class
assert_equal :exit , produced.next(27).name
assert_equal Syscall , produced.next(29).class
assert_equal :exit , produced.next(29).name
end
def test_load_address
produced = produce_body
assert_equal LoadConstant , produced.next(41).class
assert_equal Parfait::Factory , produced.next(41).constant.class
assert_equal LoadConstant , produced.next(39).class
assert_equal Parfait::Factory , produced.next(39).constant.class
end
def test_function_call
produced = produce_body
assert_equal DynamicJump , produced.next(58).class
assert_equal DynamicJump , produced.next(56).class
end
def test_cache_check
produced = produce_body
assert_equal IsZero , produced.next(6).class
assert_equal Label , produced.next(38).class
assert_equal produced.next(38) , produced.next(6).label
assert_equal Label , produced.next(36).class
assert_equal produced.next(36) , produced.next(6).label
end
end
end

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@ -7,20 +7,19 @@ module Risc
def setup
super
@input = "return @a.div4"
@expect = [LoadConstant, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg,
LoadConstant, RegToSlot, LoadConstant, LoadConstant, SlotToReg,
SlotToReg, Label, LoadConstant, OperatorInstruction, IsZero,
SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch,
Label, Transfer, Syscall, Transfer, Transfer,
LoadConstant, SlotToReg, SlotToReg, RegToSlot, RegToSlot,
RegToSlot, Label, RegToSlot, Label, LoadConstant,
SlotToReg, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
SlotToReg, LoadConstant, SlotToReg, DynamicJump, Label,
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
RegToSlot, Branch]
@expect = [LoadConstant, SlotToReg, SlotToReg, SlotToReg, SlotToReg, #5
OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg, #10
LoadConstant, RegToSlot, LoadConstant, LoadConstant, SlotToReg, #15
SlotToReg, Label, LoadConstant, OperatorInstruction, IsZero, #20
SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch, #25
Label, LoadConstant, SlotToReg, Transfer, Syscall, #30
Transfer, Transfer, SlotToReg, RegToSlot, Label, #35
RegToSlot, Label, LoadConstant, SlotToReg, LoadConstant, #40
SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot, #45
RegToSlot, SlotToReg, SlotToReg, SlotToReg, RegToSlot, #50
LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant, #55
SlotToReg, DynamicJump, Label, SlotToReg, SlotToReg, #60
RegToSlot, SlotToReg, SlotToReg, RegToSlot, Branch] #65
end
def test_return_instructions
@ -28,7 +27,7 @@ module Risc
end
def test_function_return
produced = produce_body
assert_equal Branch , produced.next(66).class
assert_equal Branch , produced.next(64).class
end
def test_cache_check
produced = produce_body