test and last fixes for previous commits (allocalte ints)

mostly just fixing the additional instructions
close #20
This commit is contained in:
Torsten Ruger 2018-11-24 22:40:22 +02:00
parent e6615d0a6a
commit 4d30727811
19 changed files with 308 additions and 233 deletions

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@ -145,6 +145,7 @@ module Risc
# We sidestep all that by pre-allocating.
def prepare_int_return
integer_tmp = allocate_int
reset_names
build do
message[:return_value] << integer_tmp
end

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@ -127,14 +127,17 @@ module Risc
end
# restore the message that we save in r8
# get a new int and save the c return into it
# the int gets retured, ie is the return_value of the message
# before th restore, the syscall return, a fixnum, is saved
# The caller of this method is assumed to caal prepare_int_return
# so that the return value already has an integer instance
# This instance is filled with os return value
def restore_message(builder)
r8 = RegisterValue.new( :r8 , :Message)
builder.build do
integer_reg! << message
message << r8
integer_tmp[Parfait::Integer.integer_index] << integer_reg
integer_2! << message[:return_value]
integer_2[Parfait::Integer.integer_index] << integer_reg
end
end

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@ -64,7 +64,9 @@ module Risc
str = all.collect{|i| i.class.name}.join(", ").gsub("Risc::","")
str = "[#{str}]"
all = str.split(",").each_slice(5).collect { |line| " " + line.join(",")}
all.join(",\n")
res = ""
all.each_with_index { |line,index| res += "#{line}, ##{index*5 + 4}\n"}
res
end
end
end

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@ -7,18 +7,18 @@ module Risc
def setup
super
@input = "@a.div4"
@expect = [LoadConstant, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg,
LoadConstant, RegToSlot, LoadConstant, LoadConstant, SlotToReg,
SlotToReg, Label, LoadConstant, OperatorInstruction, IsZero,
SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch,
Label, Transfer, Syscall, Transfer, Transfer,
LoadConstant, SlotToReg, SlotToReg, RegToSlot, RegToSlot,
RegToSlot, Label, RegToSlot, Label, LoadConstant,
SlotToReg, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
SlotToReg, LoadConstant, SlotToReg, DynamicJump, Label]
@expect = [LoadConstant, SlotToReg, SlotToReg, SlotToReg, SlotToReg, #4
OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg, #9
LoadConstant, RegToSlot, LoadConstant, LoadConstant, SlotToReg, #14
SlotToReg, Label, LoadConstant, OperatorInstruction, IsZero, #19
SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch, #24
Label, LoadConstant, SlotToReg, Transfer, Syscall, #29
Transfer, Transfer, SlotToReg, RegToSlot, Label, #34
RegToSlot, Label, LoadConstant, SlotToReg, LoadConstant, #39
SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot, #44
RegToSlot, SlotToReg, SlotToReg, SlotToReg, RegToSlot, #49
LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant, #54
SlotToReg, DynamicJump, Label]
end
def test_send_instructions
@ -26,23 +26,23 @@ module Risc
end
def test_sys
produced = produce_body
assert_equal Syscall , produced.next(27).class
assert_equal :exit , produced.next(27).name
assert_equal Syscall , produced.next(29).class
assert_equal :exit , produced.next(29).name
end
def test_load_address
produced = produce_body
assert_equal LoadConstant , produced.next(41).class
assert_equal Parfait::Factory , produced.next(41).constant.class
assert_equal LoadConstant , produced.next(39).class
assert_equal Parfait::Factory , produced.next(39).constant.class
end
def test_function_call
produced = produce_body
assert_equal DynamicJump , produced.next(58).class
assert_equal DynamicJump , produced.next(56).class
end
def test_cache_check
produced = produce_body
assert_equal IsZero , produced.next(6).class
assert_equal Label , produced.next(38).class
assert_equal produced.next(38) , produced.next(6).label
assert_equal Label , produced.next(36).class
assert_equal produced.next(36) , produced.next(6).label
end
end
end

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@ -7,20 +7,19 @@ module Risc
def setup
super
@input = "return @a.div4"
@expect = [LoadConstant, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg,
LoadConstant, RegToSlot, LoadConstant, LoadConstant, SlotToReg,
SlotToReg, Label, LoadConstant, OperatorInstruction, IsZero,
SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch,
Label, Transfer, Syscall, Transfer, Transfer,
LoadConstant, SlotToReg, SlotToReg, RegToSlot, RegToSlot,
RegToSlot, Label, RegToSlot, Label, LoadConstant,
SlotToReg, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
SlotToReg, LoadConstant, SlotToReg, DynamicJump, Label,
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
RegToSlot, Branch]
@expect = [LoadConstant, SlotToReg, SlotToReg, SlotToReg, SlotToReg, #5
OperatorInstruction, IsZero, SlotToReg, SlotToReg, SlotToReg, #10
LoadConstant, RegToSlot, LoadConstant, LoadConstant, SlotToReg, #15
SlotToReg, Label, LoadConstant, OperatorInstruction, IsZero, #20
SlotToReg, OperatorInstruction, IsZero, SlotToReg, Branch, #25
Label, LoadConstant, SlotToReg, Transfer, Syscall, #30
Transfer, Transfer, SlotToReg, RegToSlot, Label, #35
RegToSlot, Label, LoadConstant, SlotToReg, LoadConstant, #40
SlotToReg, SlotToReg, RegToSlot, RegToSlot, RegToSlot, #45
RegToSlot, SlotToReg, SlotToReg, SlotToReg, RegToSlot, #50
LoadConstant, SlotToReg, RegToSlot, SlotToReg, LoadConstant, #55
SlotToReg, DynamicJump, Label, SlotToReg, SlotToReg, #60
RegToSlot, SlotToReg, SlotToReg, RegToSlot, Branch] #65
end
def test_return_instructions
@ -28,7 +27,7 @@ module Risc
end
def test_function_return
produced = produce_body
assert_equal Branch , produced.next(66).class
assert_equal Branch , produced.next(64).class
end
def test_cache_check
produced = produce_body

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@ -0,0 +1,76 @@
require_relative "../helper"
module Risc
# Test the alloc sequence used by all integer operations
class InterpreterIntAlloc < MiniTest::Test
include Ticker
def setup
@string_input = as_main("return 5 + 5")
super
end
def test_chain
#show_base_ticks # get output of what is
check_main_chain [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg, # 10
RegToSlot, LoadConstant, SlotToReg, Branch, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, # 20
FunctionCall, LoadConstant, SlotToReg, LoadConstant, OperatorInstruction,
IsNotZero, SlotToReg, RegToSlot, SlotToReg, Branch, # 30
SlotToReg, SlotToReg, SlotToReg, SlotToReg, OperatorInstruction,
RegToSlot, RegToSlot, SlotToReg, SlotToReg, RegToSlot, # 40
LoadConstant, SlotToReg, RegToSlot, Branch, RegToSlot,
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, # 50
SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
Branch, Branch, SlotToReg, SlotToReg, RegToSlot, # 60
LoadConstant, SlotToReg, RegToSlot, RegToSlot, SlotToReg,
SlotToReg, SlotToReg, FunctionReturn, Transfer, SlotToReg, # 70
SlotToReg, Syscall, NilClass, ]
assert_equal 10 , get_return
end
def base_ticks(num)
main_ticks(22 + num)
end
def test_load_factory
lod = base_ticks( 0 )
assert_load( lod , Parfait::Factory , :r2)
assert_equal :next_integer , lod.constant.attribute_name
end
def test_slot_receiver #load next_object from factory
sl = base_ticks( 1 )
assert_slot_to_reg( sl , :r2 , 2 , :r1)
end
def test_load_nil
lod = base_ticks( 2 )
assert_load( lod , Parfait::NilClass , :r3)
end
def test_nil_check
op = base_ticks(3)
assert_equal OperatorInstruction , op.class
assert_equal :- , op.operator
assert_equal :r3 , op.left.symbol
assert_equal :r1 , op.right.symbol
assert_equal Fixnum , @interpreter.get_register(:r3).class
assert 0 != @interpreter.get_register(:r3)
end
def test_branch
br = base_ticks( 4 )
assert_equal IsNotZero , br.class
assert br.label.name.start_with?("cont_label")
end
def test_load_next_int
sl = base_ticks( 5 )
assert_slot_to_reg( sl , :r1 , 1 , :r4)
end
def test_move_next_back_to_factory
int = base_ticks( 6 )
assert_reg_to_slot( int , :r4 , :r2 , 2)
end
def test_branch_to_next_block
br = base_ticks( 8 )
assert_equal Branch , br.class
assert_equal Parfait::BinaryCode , br.label.class
end
end
end

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@ -14,40 +14,37 @@ module Risc
check_main_chain [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg, # 10
RegToSlot, LoadConstant, SlotToReg, Branch, RegToSlot,
SlotToReg, FunctionCall, SlotToReg, SlotToReg, Transfer, # 20
Transfer, LoadData, OperatorInstruction, LoadData, OperatorInstruction,
OperatorInstruction, LoadData, Transfer, OperatorInstruction, OperatorInstruction, # 30
Branch, LoadData, Transfer, OperatorInstruction, OperatorInstruction,
LoadData, Transfer, OperatorInstruction, OperatorInstruction, LoadData, # 40
OperatorInstruction, LoadData, Transfer, OperatorInstruction, Branch,
OperatorInstruction, Transfer, LoadData, OperatorInstruction, LoadData, # 50
OperatorInstruction, OperatorInstruction, LoadConstant, SlotToReg, SlotToReg,
RegToSlot, RegToSlot, RegToSlot, Branch, SlotToReg, # 60
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot,
RegToSlot, SlotToReg, SlotToReg, SlotToReg, FunctionReturn, # 70
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
RegToSlot, Branch, SlotToReg, SlotToReg, RegToSlot, # 80
Branch, LoadConstant, SlotToReg, RegToSlot, RegToSlot,
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer, # 90
SlotToReg, SlotToReg, Syscall, NilClass, ]
SlotToReg, FunctionCall, LoadConstant, SlotToReg, LoadConstant, # 20
OperatorInstruction, IsNotZero, SlotToReg, RegToSlot, SlotToReg,
Branch, SlotToReg, Transfer, Transfer, LoadData, # 30
OperatorInstruction, LoadData, OperatorInstruction, OperatorInstruction, LoadData,
Transfer, OperatorInstruction, OperatorInstruction, LoadData, Branch, # 40
Transfer, OperatorInstruction, OperatorInstruction, LoadData, Transfer,
OperatorInstruction, OperatorInstruction, LoadData, OperatorInstruction, LoadData, # 50
Transfer, OperatorInstruction, OperatorInstruction, Branch, Transfer,
LoadData, OperatorInstruction, LoadData, OperatorInstruction, OperatorInstruction, # 60
RegToSlot, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
LoadConstant, SlotToReg, Branch, RegToSlot, RegToSlot, # 70
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, SlotToReg,
SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot, # 80
Branch, SlotToReg, SlotToReg, RegToSlot, Branch,
LoadConstant, SlotToReg, RegToSlot, RegToSlot, SlotToReg, # 90
SlotToReg, SlotToReg, FunctionReturn, Transfer, SlotToReg,
SlotToReg, Syscall, NilClass, ]
assert_equal 2 , get_return
end
def test_load_space
load_ins = main_ticks 53
assert_load load_ins, Parfait::Factory
end
def test_load_to
to = main_ticks 54
assert_slot_to_reg to , :r5 , 2 ,:r2
end
def test_load_25
load_ins = main_ticks 9
assert_equal LoadConstant , load_ins.class
assert_equal 25 , @interpreter.get_register(load_ins.register).value
end
def test_load_space
load_ins = main_ticks 66
assert_load load_ins, Parfait::Factory
end
def test_return_class
ret = main_ticks(70)
ret = main_ticks(93)
assert_equal FunctionReturn , ret.class
link = @interpreter.get_register( ret.register )
assert_equal Fixnum , link.class

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@ -14,20 +14,21 @@ module Risc
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg, # 10
RegToSlot, LoadConstant, SlotToReg, Branch, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, # 20
FunctionCall, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
ByteToReg, LoadConstant, SlotToReg, SlotToReg, RegToSlot, # 30
RegToSlot, RegToSlot, SlotToReg, SlotToReg, Branch,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, RegToSlot, # 40
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, SlotToReg,
SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot, # 50
Branch, Branch, SlotToReg, SlotToReg, RegToSlot,
LoadConstant, SlotToReg, RegToSlot, RegToSlot, SlotToReg, # 60
SlotToReg, SlotToReg, FunctionReturn, Transfer, SlotToReg,
SlotToReg, Syscall, NilClass, ]
FunctionCall, LoadConstant, SlotToReg, LoadConstant, OperatorInstruction,
IsNotZero, SlotToReg, RegToSlot, SlotToReg, Branch, # 30
SlotToReg, SlotToReg, SlotToReg, ByteToReg, RegToSlot,
RegToSlot, SlotToReg, SlotToReg, RegToSlot, LoadConstant, # 40
SlotToReg, RegToSlot, RegToSlot, Branch, SlotToReg,
SlotToReg, SlotToReg, FunctionReturn, SlotToReg, SlotToReg, # 50
RegToSlot, SlotToReg, SlotToReg, RegToSlot, Branch,
Branch, SlotToReg, SlotToReg, RegToSlot, LoadConstant, # 60
SlotToReg, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
SlotToReg, FunctionReturn, Transfer, SlotToReg, SlotToReg, # 70
Syscall, NilClass, ]
assert_equal "H".ord , get_return
end
def test_byte_to_reg
done = main_ticks(26)
done = main_ticks(34)
assert_equal ByteToReg , done.class
assert_equal "H".ord , @interpreter.get_register(done.register)
end

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@ -11,41 +11,37 @@ module Risc
def test_minus
#show_main_ticks # get output of what is
check_main_chain [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
check_main_chain [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg, # 10
RegToSlot, LoadConstant, SlotToReg, Branch, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, # 20
FunctionCall, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
SlotToReg, OperatorInstruction, LoadConstant, SlotToReg, SlotToReg, # 30
RegToSlot, RegToSlot, RegToSlot, SlotToReg, Branch,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, # 40
RegToSlot, SlotToReg, SlotToReg, SlotToReg, FunctionReturn,
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, # 50
RegToSlot, Branch, Branch, SlotToReg, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, RegToSlot, # 60
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer,
SlotToReg, SlotToReg, Syscall, NilClass, ]
FunctionCall, LoadConstant, SlotToReg, LoadConstant, OperatorInstruction,
IsNotZero, SlotToReg, RegToSlot, SlotToReg, Branch, # 30
SlotToReg, SlotToReg, SlotToReg, SlotToReg, OperatorInstruction,
RegToSlot, RegToSlot, SlotToReg, SlotToReg, RegToSlot, # 40
LoadConstant, SlotToReg, RegToSlot, Branch, RegToSlot,
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, # 50
SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
Branch, Branch, SlotToReg, SlotToReg, RegToSlot, # 60
LoadConstant, SlotToReg, RegToSlot, RegToSlot, SlotToReg,
SlotToReg, SlotToReg, FunctionReturn, Transfer, SlotToReg, # 70
SlotToReg, Syscall, NilClass, ]
assert_equal 1 , get_return
end
def test_load_5
lod = main_ticks( 12 )
assert_equal LoadConstant , lod.class
assert_equal Parfait::Integer , lod.constant.class
assert_equal 5 , lod.constant.value
end
def test_op
op = main_ticks(27)
op = main_ticks(35)
assert_equal OperatorInstruction , op.class
assert_equal :r1 , op.left.symbol
assert_equal :r2 , op.right.symbol
assert_equal 1 , @interpreter.get_register(:r1)
assert_equal 5 , @interpreter.get_register(:r2)
assert_equal :- , op.operator
assert_equal :r2 , op.left.symbol
assert_equal :r3 , op.right.symbol
assert_equal 1 , @interpreter.get_register(:r2)
assert_equal 5 , @interpreter.get_register(:r3)
end
def test_return
ret = main_ticks(64)
ret = main_ticks(68)
assert_equal FunctionReturn , ret.class
assert_equal :r1 , ret.register.symbol
assert_equal 175276 , @interpreter.get_register(ret.register)
assert_equal 175116 , @interpreter.get_register(ret.register)
end
end
end

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@ -14,32 +14,28 @@ module Risc
check_main_chain [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg, # 10
RegToSlot, LoadConstant, SlotToReg, Branch, RegToSlot,
SlotToReg, FunctionCall, SlotToReg, SlotToReg, LoadData, # 20
OperatorInstruction, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, SlotToReg, SlotToReg, RegToSlot, # 30
Branch, LoadConstant, SlotToReg, RegToSlot, RegToSlot,
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, # 40
SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
Branch, SlotToReg, SlotToReg, RegToSlot, Branch, # 50
LoadConstant, SlotToReg, RegToSlot, RegToSlot, SlotToReg,
SlotToReg, SlotToReg, FunctionReturn, Transfer, SlotToReg, # 60
SlotToReg, Syscall, NilClass, ]
SlotToReg, FunctionCall, LoadConstant, SlotToReg, LoadConstant, # 20
OperatorInstruction, IsNotZero, SlotToReg, RegToSlot, SlotToReg,
Branch, SlotToReg, LoadData, OperatorInstruction, RegToSlot, # 30
RegToSlot, SlotToReg, SlotToReg, RegToSlot, LoadConstant,
SlotToReg, RegToSlot, RegToSlot, SlotToReg, Branch, # 40
SlotToReg, SlotToReg, FunctionReturn, SlotToReg, SlotToReg,
RegToSlot, SlotToReg, SlotToReg, RegToSlot, Branch, # 50
SlotToReg, SlotToReg, RegToSlot, Branch, LoadConstant,
SlotToReg, RegToSlot, RegToSlot, SlotToReg, SlotToReg, # 60
SlotToReg, FunctionReturn, Transfer, SlotToReg, SlotToReg,
Syscall, NilClass, ]
assert_equal 2 , get_return
end
def test_load
lod = main_ticks(9)
assert_equal LoadConstant , lod.class
assert_equal 9 , lod.constant.value
def test_op
op = main_ticks(29)
assert_equal OperatorInstruction , op.class
assert_equal :>> , op.operator
assert_equal :r2 , op.left.symbol
assert_equal :r3 , op.right.symbol
assert_equal 2 , @interpreter.get_register(:r2)
assert_equal 2 , @interpreter.get_register(:r3)
end
def test_fix # reduce self to fix
sl = main_ticks(19)
assert_equal SlotToReg , sl.class
assert_equal :r1 , sl.array.symbol
assert_equal 2 , sl.index
assert_equal :r1 , sl.register.symbol
assert_equal 9 , @interpreter.get_register(:r1)
end
end
end

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@ -15,16 +15,17 @@ module Risc
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg, # 10
RegToSlot, LoadConstant, SlotToReg, Branch, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, # 20
FunctionCall, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
SlotToReg, OperatorInstruction, LoadConstant, SlotToReg, SlotToReg, # 30
RegToSlot, RegToSlot, RegToSlot, SlotToReg, Branch,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, # 40
RegToSlot, SlotToReg, SlotToReg, SlotToReg, FunctionReturn,
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, # 50
RegToSlot, Branch, Branch, SlotToReg, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, RegToSlot, # 60
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer,
SlotToReg, SlotToReg, Syscall, NilClass, ]
FunctionCall, LoadConstant, SlotToReg, LoadConstant, OperatorInstruction,
IsNotZero, SlotToReg, RegToSlot, SlotToReg, Branch, # 30
SlotToReg, SlotToReg, SlotToReg, SlotToReg, OperatorInstruction,
RegToSlot, RegToSlot, SlotToReg, SlotToReg, RegToSlot, # 40
LoadConstant, SlotToReg, RegToSlot, Branch, RegToSlot,
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, # 50
SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
Branch, Branch, SlotToReg, SlotToReg, RegToSlot, # 60
LoadConstant, SlotToReg, RegToSlot, RegToSlot, SlotToReg,
SlotToReg, SlotToReg, FunctionReturn, Transfer, SlotToReg, # 70
SlotToReg, Syscall, NilClass, ]
assert_equal 0 , get_return
end
def test_zero
@ -32,15 +33,15 @@ module Risc
assert @interpreter.flags[:zero]
end
def test_op
op = main_ticks(27)
op = main_ticks(35)
assert_equal OperatorInstruction , op.class
assert_equal :r1 , op.left.symbol
assert_equal :r2 , op.right.symbol
assert_equal 0 , @interpreter.get_register(:r1)
assert_equal 2**31 , @interpreter.get_register(:r2)
assert_equal :r2 , op.left.symbol
assert_equal :r3 , op.right.symbol
assert_equal 0 , @interpreter.get_register(:r2)
assert_equal 2**31 , @interpreter.get_register(:r3)
end
def test_overflow
main_ticks( 28 )
main_ticks( 36 )
assert @interpreter.flags[:overflow]
end
end

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@ -10,79 +10,77 @@ module Risc
end
def test_chain
#show_main_ticks # get output of what is
#show_base_ticks # get output of what is
check_main_chain [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg, # 10
RegToSlot, LoadConstant, SlotToReg, Branch, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, SlotToReg, # 20
FunctionCall, SlotToReg, SlotToReg, SlotToReg, SlotToReg,
SlotToReg, OperatorInstruction, LoadConstant, SlotToReg, SlotToReg, # 30
RegToSlot, RegToSlot, RegToSlot, SlotToReg, Branch,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, RegToSlot, # 40
RegToSlot, SlotToReg, SlotToReg, SlotToReg, FunctionReturn,
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg, # 50
RegToSlot, Branch, Branch, SlotToReg, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, RegToSlot, # 60
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer,
SlotToReg, SlotToReg, Syscall, NilClass, ]
FunctionCall, LoadConstant, SlotToReg, LoadConstant, OperatorInstruction,
IsNotZero, SlotToReg, RegToSlot, SlotToReg, Branch, # 30
SlotToReg, SlotToReg, SlotToReg, SlotToReg, OperatorInstruction,
RegToSlot, RegToSlot, SlotToReg, SlotToReg, RegToSlot, # 40
LoadConstant, SlotToReg, RegToSlot, Branch, RegToSlot,
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, SlotToReg, # 50
SlotToReg, RegToSlot, SlotToReg, SlotToReg, RegToSlot,
Branch, Branch, SlotToReg, SlotToReg, RegToSlot, # 60
LoadConstant, SlotToReg, RegToSlot, RegToSlot, SlotToReg,
SlotToReg, SlotToReg, FunctionReturn, Transfer, SlotToReg, # 70
SlotToReg, Syscall, NilClass, ]
assert_equal 10 , get_return
end
def base_ticks(num)
main_ticks(22 + num)
end
def test_load_5
lod = main_ticks( 12 )
assert_load( lod , Parfait::Integer , :r1)
assert_equal 5 , lod.constant.value
end
def base
22
def test_load_receiver
sl = base_ticks( 7 )
assert_slot_to_reg( sl , :r0 , 2 , :r2)
end
def test_slot_receiver #load receiver from message
sl = main_ticks( base )
assert_slot_to_reg( sl , :r0 , 2 , :r1)
def test_reduce_receiver
sl = base_ticks( 9 )
assert_slot_to_reg( sl , :r2 , 2 , :r2)
end
def test_slot_args #load args from message
sl = main_ticks( base + 1 )
assert_slot_to_reg( sl , :r0 , 8 , :r2)
sl = base_ticks( 10 )
assert_slot_to_reg( sl , :r0 , 8 , :r3)
end
def test_slot_arg_int #load arg 1, destructively from args
sl = main_ticks( base + 2 )
assert_slot_to_reg( sl , :r2 , 1 , :r2)
sl = base_ticks( 11 )
assert_slot_to_reg( sl , :r3 , 1 , :r3)
end
def test_slot_int1 #load int from object
sl = main_ticks( base + 3 )
assert_slot_to_reg( sl , :r1 , 2 , :r1)
assert_equal 5 , @interpreter.get_register(:r1)
end
def test_slot_int2 #load int from object
sl = main_ticks( base + 4 )
assert_slot_to_reg( sl , :r2 , 2 , :r2)
assert_equal 5 , @interpreter.get_register(:r2)
def test_reduce_arg
sl = base_ticks( 12 )
assert_slot_to_reg( sl , :r3 , 2 , :r3)
assert_equal 5 , @interpreter.get_register(:r3)
end
def test_op
op = main_ticks(base + 5)
op = base_ticks(13)
assert_equal OperatorInstruction , op.class
assert_equal :+ , op.operator
assert_equal :r1 , op.left.symbol
assert_equal :r2 , op.right.symbol
assert_equal 10 , @interpreter.get_register(:r1)
assert_equal 5 , @interpreter.get_register(:r2)
assert_equal :r2 , op.left.symbol
assert_equal :r3 , op.right.symbol
assert_equal 10 , @interpreter.get_register(:r2)
assert_equal 5 , @interpreter.get_register(:r3)
end
def test_load_int_space
cons = main_ticks(base + 6)
assert_load( cons , Parfait::Factory , :r3)
def test_move_res_to_int
int = base_ticks( 14 )
assert_reg_to_slot( int , :r2 , :r1 , 2)
end
def test_load_int_next_space
sl = main_ticks(base + 7)
assert_slot_to_reg( sl , :r3 , 2 , :r2)
assert_equal Parfait::Integer , @interpreter.get_register(:r2).class
def test_move_int_to_reg
int = base_ticks( 15 )
assert_reg_to_slot( int , :r1 , :r0 , 5)
end
def test_load_int_next_int
sl = main_ticks(base + 8)
assert_slot_to_reg( sl , :r2 , 1 , :r4)
assert_equal Parfait::Integer , @interpreter.get_register(:r4).class
def test_move_fix_to_result
sl = base_ticks( 16 )
assert_slot_to_reg( sl , :r0 , 5 , :r1)
end
def test_load_int_next_int2
sl = main_ticks(base + 9)
assert_reg_to_slot( sl , :r4 , :r3 , 2)
def test_start_return_sequence
sl = base_ticks( 17 )
assert_slot_to_reg( sl , :r0 , 6 , :r2)
end
end
end

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@ -14,16 +14,17 @@ module Risc
check_main_chain [LoadConstant, LoadConstant, SlotToReg, SlotToReg, RegToSlot,
RegToSlot, RegToSlot, RegToSlot, LoadConstant, SlotToReg, # 10
RegToSlot, LoadConstant, SlotToReg, Branch, RegToSlot,
SlotToReg, FunctionCall, SlotToReg, SlotToReg, Transfer, # 20
Syscall, Transfer, Transfer, LoadConstant, SlotToReg,
SlotToReg, RegToSlot, RegToSlot, RegToSlot, SlotToReg, # 30
Branch, SlotToReg, RegToSlot, LoadConstant, SlotToReg,
RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg, # 40
FunctionReturn, SlotToReg, SlotToReg, RegToSlot, SlotToReg,
SlotToReg, RegToSlot, Branch, SlotToReg, SlotToReg, # 50
RegToSlot, Branch, LoadConstant, SlotToReg, RegToSlot,
RegToSlot, SlotToReg, SlotToReg, SlotToReg, FunctionReturn, # 60
Transfer, SlotToReg, SlotToReg, Syscall, NilClass, ]
SlotToReg, FunctionCall, LoadConstant, SlotToReg, LoadConstant, # 20
OperatorInstruction, IsNotZero, SlotToReg, RegToSlot, RegToSlot,
Branch, SlotToReg, SlotToReg, Transfer, Syscall, # 30
Transfer, Transfer, SlotToReg, RegToSlot, SlotToReg,
SlotToReg, RegToSlot, LoadConstant, SlotToReg, Branch, # 40
RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg,
FunctionReturn, SlotToReg, SlotToReg, RegToSlot, SlotToReg, # 50
SlotToReg, RegToSlot, Branch, SlotToReg, SlotToReg,
RegToSlot, Branch, LoadConstant, SlotToReg, RegToSlot, # 60
RegToSlot, SlotToReg, SlotToReg, SlotToReg, FunctionReturn,
Transfer, SlotToReg, SlotToReg, Syscall, NilClass, ] # 70
assert_equal "Hello again" , @interpreter.stdout
assert_equal 11 , get_return #bytes written
end
@ -34,7 +35,7 @@ module Risc
end
def test_putstring_sys
done = main_ticks(21)
done = main_ticks(30)
assert_equal Syscall , done.class
assert_equal "Hello again" , @interpreter.stdout
assert_equal 11 , @interpreter.get_register(:r0)
@ -42,21 +43,21 @@ module Risc
assert_equal "Hello again" , @interpreter.get_register(:r1).to_string
end
def test_move_sys_return
sl = main_ticks(22)
assert_transfer(sl, :r0 ,:r4)
assert_equal 11 , @interpreter.get_register(:r4)
sl = main_ticks(31)
assert_transfer(sl, :r0 ,:r3)
assert_equal 11 , @interpreter.get_register(:r3)
end
def test_restore_message
sl = main_ticks(23)
sl = main_ticks(32)
assert_transfer(sl, :r8 ,:r0)
assert_equal Parfait::Message , @interpreter.get_register(:r0).class
end
def test_save_sys_return
sl = main_ticks(28)
assert_reg_to_slot( sl , :r4 ,:r3 , 2)
def test_move_sys_return
sl = main_ticks(37)
assert_reg_to_slot( sl , :r1 ,:r2 , 5)
end
def test_return
done = main_ticks(60)
done = main_ticks(65)
assert_equal FunctionReturn , done.class
end

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@ -16,20 +16,19 @@ module Risc
RegToSlot, LoadConstant, SlotToReg, Branch, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, SlotToReg, RegToSlot, # 20
LoadConstant, SlotToReg, RegToSlot, SlotToReg, FunctionCall,
SlotToReg, SlotToReg, SlotToReg, SlotToReg, SlotToReg, # 30
SlotToReg, SlotToReg, SlotToReg, RegToByte, RegToSlot,
SlotToReg, SlotToReg, RegToSlot, Branch, LoadConstant, # 40
SlotToReg, RegToSlot, RegToSlot, SlotToReg, SlotToReg,
SlotToReg, FunctionReturn, SlotToReg, SlotToReg, Branch, # 50
RegToSlot, SlotToReg, SlotToReg, RegToSlot, Branch,
SlotToReg, SlotToReg, RegToSlot, LoadConstant, SlotToReg, # 60
RegToSlot, RegToSlot, SlotToReg, Branch, SlotToReg,
SlotToReg, FunctionReturn, Transfer, SlotToReg, SlotToReg, # 70
Syscall, NilClass, ]
SlotToReg, SlotToReg, SlotToReg, RegToSlot, SlotToReg, # 30
SlotToReg, SlotToReg, RegToByte, SlotToReg, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, Branch, RegToSlot, # 40
RegToSlot, SlotToReg, SlotToReg, SlotToReg, FunctionReturn,
SlotToReg, SlotToReg, Branch, RegToSlot, SlotToReg, # 50
SlotToReg, RegToSlot, Branch, SlotToReg, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, RegToSlot, # 60
SlotToReg, Branch, SlotToReg, SlotToReg, FunctionReturn,
Transfer, SlotToReg, SlotToReg, Syscall, NilClass, ]
assert_equal "K".ord , get_return
end
def test_reg_to_byte
done = main_ticks(34)
done = main_ticks(33)
assert_equal RegToByte , done.class
assert_equal "K".ord , @interpreter.get_register(done.register)
end

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@ -25,19 +25,20 @@ module Risc
Branch, LoadConstant, OperatorInstruction, IsZero, SlotToReg, # 60
OperatorInstruction, IsZero, SlotToReg, Branch, Branch,
LoadConstant, OperatorInstruction, IsZero, SlotToReg, OperatorInstruction, # 70
IsZero, RegToSlot, LoadConstant, Branch, SlotToReg,
LoadConstant, SlotToReg, SlotToReg, RegToSlot, RegToSlot, # 80
IsZero, RegToSlot, LoadConstant, SlotToReg, LoadConstant,
Branch, SlotToReg, SlotToReg, RegToSlot, RegToSlot, # 80
RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg,
RegToSlot, LoadConstant, Branch, SlotToReg, RegToSlot, # 90
SlotToReg, LoadConstant, SlotToReg, DynamicJump, SlotToReg,
SlotToReg, LoadData, OperatorInstruction, LoadConstant, SlotToReg, # 100
SlotToReg, RegToSlot, RegToSlot, RegToSlot, SlotToReg,
SlotToReg, RegToSlot, Branch, LoadConstant, SlotToReg, # 110
RegToSlot, RegToSlot, SlotToReg, SlotToReg, SlotToReg,
FunctionReturn, SlotToReg, SlotToReg, RegToSlot, SlotToReg, # 120
SlotToReg, RegToSlot, Branch, SlotToReg, SlotToReg,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, RegToSlot, # 130
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer,
RegToSlot, LoadConstant, SlotToReg, RegToSlot, Branch, # 90
SlotToReg, LoadConstant, SlotToReg, DynamicJump, LoadConstant,
SlotToReg, LoadConstant, OperatorInstruction, IsNotZero, SlotToReg, # 100
RegToSlot, SlotToReg, Branch, SlotToReg, LoadData,
OperatorInstruction, RegToSlot, RegToSlot, SlotToReg, SlotToReg, # 110
RegToSlot, LoadConstant, SlotToReg, RegToSlot, RegToSlot,
SlotToReg, Branch, SlotToReg, SlotToReg, FunctionReturn, # 120
SlotToReg, SlotToReg, RegToSlot, SlotToReg, SlotToReg,
RegToSlot, Branch, SlotToReg, SlotToReg, Branch, # 130
RegToSlot, LoadConstant, SlotToReg, RegToSlot, RegToSlot,
SlotToReg, SlotToReg, SlotToReg, FunctionReturn, Transfer, # 140
SlotToReg, SlotToReg, Syscall, NilClass, ]
assert_equal Fixnum , get_return.class
assert_equal 1 , get_return
@ -59,13 +60,13 @@ module Risc
assert_equal DynamicJump , cal.class
end
def test_return
ret = main_ticks(134)
ret = main_ticks(139)
assert_equal FunctionReturn , ret.class
link = @interpreter.get_register( ret.register )
assert_equal Fixnum , link.class
end
def test_sys
sys = main_ticks(138)
sys = main_ticks(143)
assert_equal Syscall , sys.class
end
end

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@ -32,6 +32,10 @@ module Risc
assert_equal :Integer , @builder.space.type.class_name
assert_equal :Space , @builder.integer.type.class_name
end
def test_prepare_int
int = @builder.prepare_int_return
assert_raises { @builder.integer_tmp}
end
def test_allocate_returns
int = @builder.allocate_int
assert_equal :r1 , int.symbol

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@ -12,7 +12,7 @@ module Risc
assert @branch.to_s.include?("test")
end
def test_branch_tos2
branch = Branch.new(nil ,nil)
branch = Branch.new(nil ,@label)
assert branch.to_s.include?("Branch")
end
def test_label_tos1

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@ -54,7 +54,7 @@ module Risc
end
def test_pc1
@interpreter.tick
assert_equal 174632 , @interpreter.pc
assert_equal 174552 , @interpreter.pc
end
def test_tick2
@interpreter.tick
@ -68,7 +68,7 @@ module Risc
def test_pc2
@interpreter.tick
@interpreter.tick
assert_equal 174636 , @interpreter.pc
assert_equal 174556 , @interpreter.pc
end
def test_tick_14_jump
14.times {@interpreter.tick}

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@ -25,7 +25,7 @@ module Risc
assert_equal 0 , Position.get(@linker.cpu_init).at
end
def test_cpu_at
assert_equal "0x2b91c" , Position.get(@linker.cpu_init.first).to_s
assert_equal "0x2b90c" , Position.get(@linker.cpu_init.first).to_s
end
def test_cpu_label
assert_equal Position , Position.get(@linker.cpu_init.first).class