ruby-x/rubyx
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

folded salama-arm in

Browse Source
This commit is contained in:
Torsten Ruger
2016-12-14 13:43:13 +02:00
parent 56032c9b08
commit 456e9b1ec0
22 changed files with 1372 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

113
lib/arm/arm_machine.rb Normal file
View File

@ -0,0 +1,113 @@
require_relative "attributed"
module Arm
# A Machines main responsibility in the framework is to instantiate Instructions
# Value functions are mapped to machines by concatenating the values class name + the methd name
# Example: IntegerValue.plus( value ) -> Machine.signed_plus (value )
# Also, shortcuts are created to easily instantiate Instruction objects.
# Example: pop -> StackInstruction.new( {:opcode => :pop}.merge(options) )
# Instructions work with options, so you can pass anything in, and the only thing the functions
# does is save you typing the clazz.new. It passes the function name as the :opcode
class ArmMachine
# conditions specify all the possibilities for branches. Branches are b + condition
# Example: beq means brach if equal.
# :al means always, so bal is an unconditional branch (but b() also works)
CONDITIONS = [:al ,:eq ,:ne ,:lt ,:le ,:ge,:gt ,:cs ,:mi ,:hi ,:cc ,:pl,:ls ,:vc ,:vs]
# here we create the shortcuts for the "standard" instructions, see above
# Derived machines may use own instructions and define functions for them if so desired
def self.init
[:push, :pop].each do |inst|
define_instruction_one(inst , StackInstruction)
end
[:adc, :add, :and, :bic, :eor, :orr, :rsb, :rsc, :sbc, :sub , :mul].each do |inst|
define_instruction_three(inst , LogicInstruction)
end
[:mov, :mvn].each do |inst|
define_instruction_two(inst , MoveInstruction)
end
[:cmn, :cmp, :teq, :tst].each do |inst|
define_instruction_two(inst , CompareInstruction)
end
[:strb, :str , :ldrb, :ldr].each do |inst|
define_instruction_three(inst , MemoryInstruction)
end
[:b, :call , :swi].each do |inst|
define_instruction_one(inst , CallInstruction)
end
# create all possible brach instructions, but the CallInstruction demangles the
# code, and has opcode set to :b and :condition_code set to the condition
CONDITIONS.each do |suffix|
define_instruction_one("b#{suffix}".to_sym , CallInstruction)
define_instruction_one("call#{suffix}".to_sym , CallInstruction)
end
end
def self.create_method(name, &block)
self.class.send(:define_method, name , &block)
end
def self.class_for clazz
my_module = self.class.name.split("::").first
clazz_name = clazz.name.split("::").last
if(my_module != Register )
module_class = eval("#{my_module}::#{clazz_name}") rescue nil
clazz = module_class if module_class
end
clazz
end
#defining the instruction (opcode, symbol) as an given class.
# the class is a Register::Instruction derived base class and to create machine specific function
# an actual machine must create derived classes (from this base class)
# These instruction classes must follow a naming pattern and take a hash in the contructor
# Example, a mov() opcode instantiates a Register::MoveInstruction
# for an Arm machine, a class Arm::MoveInstruction < Register::MoveInstruction exists, and it
# will be used to define the mov on an arm machine.
# This methods picks up that derived class and calls a define_instruction methods that can
# be overriden in subclasses
def self.define_instruction_one(inst , clazz , defaults = {} )
clazz = class_for(clazz)
create_method(inst) do |first , options = nil|
options = {} if options == nil
options.merge defaults
options[:opcode] = inst
first = Register::RegisterValue.convert(first)
clazz.new(first , options)
end
end
# same for two args (left right, from to etc)
def self.define_instruction_two(inst , clazz , defaults = {} )
clazz = self.class_for(clazz)
create_method(inst) do |left ,right , options = nil|
options = {} if options == nil
options.merge defaults
left = Register::RegisterValue.convert(left)
right = Register::RegisterValue.convert(right)
options[:opcode] = inst
clazz.new(left , right ,options)
end
end
# same for three args (result = left right,)
def self.define_instruction_three(inst , clazz , defaults = {} )
clazz = self.class_for(clazz)
create_method(inst) do |result , left ,right = nil , options = nil|
options = {} if options == nil
options.merge defaults
options[:opcode] = inst
result = Register::RegisterValue.convert(result)
left = Register::RegisterValue.convert(left)
right = Register::RegisterValue.convert(right)
clazz.new(result, left , right ,options)
end
end
end
end
Arm::ArmMachine.init

38
lib/arm/attributed.rb Normal file
View File

@ -0,0 +1,38 @@
module Arm
# The arm machine has following instruction classes
# - Memory
# - Stack
# - Logic
# - Math
# - Control/Compare
# - Move
# - Call class Instruction
module Attributed
attr_reader :attributes
def opcode
@attributes[:opcode]
end
def set_opcode code
@attributes[:opcode] = code
end
# for the shift handling that makes the arm so unique
def shift val , by
raise "Not integer #{val}:#{val.class} #{inspect}" unless val.is_a? Fixnum
val << by
end
def byte_length
4
end
end
end
require_relative "constants"
require_relative "instructions/call_instruction"
require_relative "instructions/compare_instruction"
require_relative "instructions/logic_instruction"
require_relative "instructions/memory_instruction"
require_relative "instructions/move_instruction"
require_relative "instructions/stack_instruction"

135
lib/arm/constants.rb Normal file
View File

@ -0,0 +1,135 @@
module Arm
module Constants
OPCODES = {
:adc => 0b0101, :add => 0b0100,
:and => 0b0000, :bic => 0b1110,
:eor => 0b0001, :orr => 0b1100,
:rsb => 0b0011, :rsc => 0b0111,
:sbc => 0b0110, :sub => 0b0010,
:mul => 0b0000 , # reverse engineered, shoud check
# for these Rn is sbz (should be zero)
:mov => 0b1101,
:mvn => 0b1111,
# for these Rd is sbz and S=1
:cmn => 0b1011,
:cmp => 0b1010,
:teq => 0b1001,
:tst => 0b1000,
:b => 0b1010,
:call=> 0b1011
}
#return the bit patter that the cpu uses for the current instruction @attributes[:opcode]
def op_bit_code
bit_code = OPCODES[opcode]
bit_code or raise "no code found for #{opcode} #{inspect}"
end
#codition codes can be applied to many instructions and thus save branches
# :al => always , :eq => equal and so on
# eq mov if equal :moveq r1 r2 (also exists as function) will only execute
# if the last operation was 0
COND_CODES = {
:al => 0b1110, :eq => 0b0000,
:ne => 0b0001, :cs => 0b0010,
:mi => 0b0100, :hi => 0b1000,
:cc => 0b0011, :pl => 0b0101,
:ls => 0b1001, :vc => 0b0111,
:lt => 0b1011, :le => 0b1101,
:ge => 0b1010, :gt => 0b1100,
:vs => 0b0110
}
# return the bit pattern for the @attributes[:condition_code] variable,
# which signals the conditional code
def cond_bit_code
COND_CODES[@attributes[:condition_code]] or throw "no code found for #{@attributes[:condition_code]}"
end
REGISTERS = { 'r0' => 0, 'r1' => 1, 'r2' => 2, 'r3' => 3, 'r4' => 4, 'r5' => 5,
'r6' => 6, 'r7' => 7, 'r8' => 8, 'r9' => 9, 'r10' => 10, 'r11' => 11,
'r12' => 12, 'r13' => 13, 'r14' => 14, 'r15' => 15, 'a1' => 0, 'a2' => 1,
'a3' => 2, 'a4' => 3, 'v1' => 4, 'v2' => 5, 'v3' => 6, 'v4' => 7, 'v5' => 8,
'v6' => 9, 'rfp' => 9, 'sl' => 10, 'fp' => 11, 'ip' => 12, 'sp' => 13,
'lr' => 14, 'pc' => 15 }
def reg r_name
code = reg_code r_name
raise "no such register #{r_name}" unless code
Arm::Register.new(r_name.to_sym , code )
end
def reg_code r_name
raise "double r #{r_name}" if( :rr1 == r_name)
if r_name.is_a? ::Register::RegisterValue
r_name = r_name.symbol
end
if r_name.is_a? Fixnum
r_name = "r#{r_name}"
end
r = REGISTERS[r_name.to_s]
raise "no reg #{r_name}" if r == nil
r
end
def calculate_u8_with_rr(arg)
parts = arg.to_s(2).rjust(32,'0').scan(/^(0*)(.+?)0*$/).flatten
pre_zeros = parts[0].length
imm_len = parts[1].length
if ((pre_zeros+imm_len) % 2 == 1)
u8_imm = (parts[1]+'0').to_i(2)
imm_len += 1
else
u8_imm = parts[1].to_i(2)
end
if u8_imm.fits_u8?
# can do!
rot_imm = (pre_zeros+imm_len) / 2
if (rot_imm > 15)
return nil
end
return u8_imm | (rot_imm << 8)
else
return nil
end
end
Register::RegisterValue.class_eval do
def reg_no
@symbol.to_s[1 .. -1].to_i
end
end
#slighly wrong place for this code, but since the module gets included in instructions anyway . . .
# implement the barrel shifter on the operand (which is set up before as an integer)
def shift_handling
op = 0
#codes that one can shift, first two probably most common.
# l (in lsr) means logical, ie unsigned, a (in asr) is arithmetic, ie signed
shift_codes = {'lsl' => 0b000, 'lsr' => 0b010, 'asr' => 0b100, 'ror' => 0b110, 'rrx' => 0b110}
shift_codes.each do |short, bin|
long = "shift_#{short}".to_sym
if shif = @attributes[long]
# TODO need more tests
if (shif.is_a?(Numeric))
raise "0 < shift <= 32 #{shif} #{inspect}" if (shif >= 32) or( shif < 0)
op |= shift(bin , 4 )
op |= shift(shif , 4+3)
else
bin |= 0x1;
op |= shift(bin , 4 )
op |= shift(shif.reg_no , 8)
end
break
end
end
return op
end
# arm intrucioons are pretty sensible, and always 4 bytes (thumb not supported)
def byte_length
4
end
end
end

94
lib/arm/instructions/call_instruction.rb Normal file
View File

@ -0,0 +1,94 @@
module Arm
# There are only three call instructions in arm branch (b), call (bl) and syscall (swi)
# A branch could be called a jump as it has no notion of returning
# The pc is put into the link register to make a return possible
# a return is affected by moving the stored link register into the pc, effectively a branch
# swi (SoftWareInterrupt) or system call is how we call the kernel.
# in Arm the register layout is different and so we have to place the syscall code into register 7
# Registers 0-6 hold the call values as for a normal c call
class CallInstruction < Register::Branch
include Constants
include Attributed
def initialize(first, attributes)
super(nil, nil)
@attributes = attributes
raise "no target" if first.nil?
@first = first
opcode = @attributes[:opcode].to_s
if opcode.length == 3 and opcode[0] == "b"
@attributes[:condition_code] = opcode[1,2].to_sym
@attributes[:opcode] = :b
end
if opcode.length == 6 and opcode[0] == "c"
@attributes[:condition_code] = opcode[4,2].to_sym
@attributes[:opcode] = :call
end
@attributes[:update_status] = 0
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
end
def assemble(io)
case @attributes[:opcode]
when :b, :call
arg = @first
if arg.is_a?(Register::Label) or arg.is_a?(Parfait::TypedMethod)
#relative addressing for jumps/calls
# but because of the arm "theoretical" 3- stage pipeline,
# we have to subtract 2 words (fetch/decode)
if(arg.is_a? Register::Label)
diff = arg.position - self.position - 8
else
# But, for methods, this happens to be the size of the object header,
# so there it balances out, but not blocks
# have to use the code, not the mthod object for methods
diff = arg.binary.position - self.position
end
arg = diff
end
if (arg.is_a?(Numeric))
jmp_val = arg >> 2
packed = [jmp_val].pack('l')
# signed 32-bit, condense to 24-bit
# TODO add check that the value fits into 24 bits
io << packed[0,3]
else
raise "else not Attributed arg =\n#{arg.to_s[0..1000]}: #{inspect[0..1000]}"
end
io.write_uint8 op_bit_code | (COND_CODES[@attributes[:condition_code]] << 4)
when :swi
arg = @first
if (arg.is_a?(Numeric))
packed = [arg].pack('L')[0,3]
io << packed
io.write_uint8 0b1111 | (COND_CODES[@attributes[:condition_code]] << 4)
else
raise "invalid operand argument expected literal not #{arg} #{inspect}"
end
else
raise "Should not be the case #{inspect}"
end
end
def uses
if opcode == :call
@first.args.collect {|arg| arg.register }
else
[]
end
end
def assigns
if opcode == :call
[RegisterValue.new(RegisterMachine.instance.return_register)]
else
[]
end
end
def to_s
"#{opcode} #{@first} #{super}"
end
end
end

103
lib/arm/instructions/compare_instruction.rb Normal file
View File

@ -0,0 +1,103 @@
module Arm
class CompareInstruction < Register::Instruction
include Constants
include Attributed
def initialize(left , right , attributes)
super(nil)
@attributes = attributes
@left = left
@right = right.is_a?(Fixnum) ? IntegerConstant.new(right) : right
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@operand = 0
@immediate = 0
@attributes[:update_status] = 1
@rn = left
@rd = :r0
end
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
rn = @rn
operand = @operand
immediate = @immediate
arg = @right
if arg.is_a?(Parfait::Object)
# do pc relative addressing with the difference to the instuction
# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
arg = arg.position - self.position - 8
rn = :pc
end
if( arg.is_a? Symbol )
arg = Register::RegisterValue.new( arg , :Integer)
end
if (arg.is_a?(Numeric))
if (arg.fits_u8?)
# no shifting needed
operand = arg
immediate = 1
elsif (op_with_rot = calculate_u8_with_rr(arg))
operand = op_with_rot
immediate = 1
raise "hmm"
else
raise "cannot fit numeric literal argument in operand #{arg.inspect}"
end
elsif (arg.is_a?(Symbol) or arg.is_a?(::Register::RegisterValue))
operand = arg
immediate = 0
elsif (arg.is_a?(Arm::Shift))
rm_ref = arg.argument
immediate = 0
shift_op = {'lsl' => 0b000, 'lsr' => 0b010, 'asr' => 0b100,
'ror' => 0b110, 'rrx' => 0b110}[arg.type]
if (arg.type == 'ror' and arg.value.nil?)
# ror #0 == rrx
raise "cannot rotate by zero #{arg} #{inspect}"
end
arg1 = arg.value
if (arg1.is_a?(Register::IntegerConstant))
if (arg1.value >= 32)
raise "cannot shift by more than 31 #{arg1} #{inspect}"
end
shift_imm = arg1.value
elsif (arg1.is_a?(Arm::Register))
shift_op val |= 0x1;
shift_imm = arg1.number << 1
elsif (arg.type == 'rrx')
shift_imm = 0
end
operand = rm_ref | (shift_op << 4) | (shift_imm << 4+3)
else
raise "invalid operand argument #{arg.inspect} , #{inspect}"
end
instuction_class = 0b00 # OPC_DATA_PROCESSING
val = (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterValue)) ? reg_code(operand) : operand
val = 0 if val == nil
val = shift(val , 0)
raise inspect unless reg_code(@rd)
val |= shift(reg_code(@rd) , 12)
val |= shift(reg_code(rn) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 +1)
val |= shift(immediate , 12+4+4 +1+4)
val |= shift(instuction_class , 12+4+4 +1+4+1)
val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
io.write_uint32 val
end
def uses
ret = [@left.register ]
ret << @right.register unless @right.is_a? Constant
ret
end
def assigns
[]
end
def to_s
"#{opcode} #{@left} , #{@right} #{super}"
end
end
end

121
lib/arm/instructions/logic_instruction.rb Normal file
View File

@ -0,0 +1,121 @@
module Arm
class LogicInstruction < Register::Instruction
include Constants
include Attributed
# result = left op right
#
# Logic instruction are your basic operator implementation. But unlike the (normal) code we write
# these Instructions must have "place" to write their results. Ie when you write 4 + 5 in ruby
# the result is sort of up in the air, but with Instructions the result must be assigned
def initialize(result , left , right , attributes = {})
super(nil)
@attributes = attributes
@result = result
@left = left
@right = right
@attributes[:update_status] = 1 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@operand = 0
raise "Left arg must be given #{inspect}" unless @left
@immediate = 0
end
attr_accessor :result , :left , :right
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
left = @left
operand = @operand
immediate = @immediate
right = @right
if( @left.is_a?(Parfait::Object) or @left.is_a?(Register::Label) or
(@left.is_a?(Symbol) and !Register::RegisterValue.look_like_reg(@left)))
# do pc relative addressing with the difference to the instuction
# 8 is for the funny pipeline adjustment (ie pointing to fetch and not execute)
right = @left.position - self.position - 8
if( (right < 0) && ((opcode == :add) || (opcode == :sub)) )
right *= -1 # this works as we never issue sub only add
set_opcode :sub # so (as we can't change the sign permanently) we can change the opcode
end # and the sign even for sub (becuase we created them)
raise "No negatives implemented #{self} #{right} " if right < 0
left = :pc
end
if (right.is_a?(Numeric))
if (right.fits_u8?)
# no shifting needed
operand = right
immediate = 1
elsif (op_with_rot = calculate_u8_with_rr(right))
operand = op_with_rot
immediate = 1
else
#TODO this is copied from MoveInstruction, should rework
unless @extra
@extra = 1
#puts "RELINK L at #{self.position.to_s(16)}"
raise ::Register::LinkException.new("cannot fit numeric literal argument in operand #{right.inspect}")
end
# now we can do the actual breaking of instruction, by splitting the operand
first = right & 0xFFFFFF00
operand = calculate_u8_with_rr( first )
raise "no fit for #{right}" unless operand
immediate = 1
# use sub for sub and add for add, ie same as opcode
@extra = ArmMachine.send( opcode , result , result , (right & 0xFF) )
end
elsif (right.is_a?(Symbol) or right.is_a?(::Register::RegisterValue))
operand = reg_code(right) #integer means the register the integer is in (otherwise constant)
immediate = 0 # ie not immediate is register
else
raise "invalid operand argument #{right.inspect} , #{inspect}"
end
result = reg_code(@result)
left_code = reg_code(left)
op = shift_handling
instuction_class = 0b00 # OPC_DATA_PROCESSING
if( opcode == :mul )
operand = reg_code(left) + 0x90
op = reg_code(right) << 8
result = 0
left_code = reg_code(@result)
end
val = shift(operand , 0)
val |= shift(op , 0) # any barrel action, is already shifted
val |= shift(result , 12)
val |= shift(left_code , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 + 1)
val |= shift(immediate , 12+4+4 + 1+4)
val |= shift(instuction_class , 12+4+4 + 1+4+1)
val |= shift(cond_bit_code , 12+4+4 + 1+4+1+2)
io.write_uint32 val
# by now we have the extra add so assemble that
if(@extra)
if(@extra == 1) # unles things have changed and then we add a noop (to keep the length same)
@extra = ArmMachine.mov( :r1 , :r1 )
end
@extra.assemble(io)
#puts "Assemble extra at #{val.to_s(16)}"
end
end
def byte_length
@extra ? 8 : 4
end
def to_s
"#{self.class.name} #{opcode} #{@result} = #{@left} #{@right} extra=#{@extra}"
end
def uses
ret = []
ret << @left.register if @left and not @left.is_a? Constant
ret << @right.register if @right and not @right.is_a?(Constant)
ret
end
def assigns
[@result.register]
end
end
end

121
lib/arm/instructions/memory_instruction.rb Normal file
View File

@ -0,0 +1,121 @@
module Arm
# ADDRESSING MODE 2
# Implemented: immediate offset with offset=0
class MemoryInstruction < Register::Instruction
include Constants
include Attributed
def initialize result , left , right = nil , attributes = {}
super(nil)
@attributes = attributes
@result = result
@left = left
@right = right
@attributes[:update_status] = 1 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@operand = 0
raise "alert" if right.is_a? Register::Label
@pre_post_index = 0 #P flag
@add_offset = 0 #U flag
@is_load = opcode.to_s[0] == "l" ? 1 : 0 #L (load) flag
end
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
rn = @rn
operand = @operand
add_offset = @add_offset
arg = @left
arg = arg.symbol if( arg.is_a? ::Register::RegisterValue )
#str / ldr are _serious instructions. With BIG possibilities not half are implemented
is_reg = arg.is_a?(::Register::RegisterValue)
if( arg.is_a?(Symbol) and not is_reg)
is_reg = (arg.to_s[0] == "r")
end
if (is_reg ) #symbol is register
rn = arg
if @right
operand = @right
#TODO better test, this operand integer (register) does not work. but sleep first
operand = operand.symbol if operand.is_a? ::Register::RegisterValue
unless( operand.is_a? Symbol)
#puts "operand #{operand.inspect}"
if (operand < 0)
add_offset = 0
#TODO test/check/understand
operand *= -1
else
add_offset = 1
end
if (@operand.abs > 4095)
raise "reference offset too large/small (max 4095) #{arg} #{inspect}"
end
end
end
elsif (arg.is_a?(Parfait::Object) or arg.is_a? Symbol ) #use pc relative
rn = :pc
operand = arg.position - self.position - 8 #stringtable is after code
add_offset = 1
if (operand.abs > 4095)
raise "reference offset too large/small (4095<#{operand}) #{arg} #{inspect}"
end
elsif( arg.is_a?(Numeric) )
#TODO untested branch, probably not working
raise "is this working ?? #{arg} #{inspect}"
@pre_post_index = 1
@rn = pc
@use_addrtable_reloc = true
@addrtable_reloc_target = arg
else
raise "invalid operand argument #{arg.inspect} #{inspect}"
end
#not sure about these 2 constants. They produce the correct output for str r0 , r1
# but i can't help thinking that that is because they are not used in that instruction and
# so it doesn't matter. Will see
add_offset = 1
# TODO to be continued
add_offset = 0 if @attributes[:add_offset]
@pre_post_index = 1
@pre_post_index = 0 if @attributes[:pre_post_index]
w = 0 #W flag
byte_access = opcode.to_s[-1] == "b" ? 1 : 0 #B (byte) flag
instuction_class = 0b01 # OPC_MEMORY_ACCESS
if (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterValue))
val = reg_code(operand)
@pre_post_index = 0
i = 1 # not quite sure about this, but it gives the output of as. read read read.
else
i = 0 #I flag (third bit)
val = operand
end
# testing against gnu as, setting the flag produces correct output
# but gnu as produces same output for auto_inc or not, so that seems broken
# luckily auto_inc is not used and even if it clobbers unused reg in soml, but still
@pre_post_index = 1
op = shift_handling
val = shift(val , 0 ) # for the test
val |= shift(op , 0)
val |= shift(reg_code(@result) , 12 )
val |= shift(reg_code(rn) , 12+4) #16
val |= shift(@is_load , 12+4 +4)
val |= shift(w , 12+4 +4+1)
val |= shift(byte_access , 12+4 +4+1+1)
val |= shift(add_offset , 12+4 +4+1+1+1)
val |= shift(@pre_post_index, 12+4 +4+1+1+1+1)#24
val |= shift(i , 12+4 +4+1+1+1+1 +1)
val |= shift(instuction_class,12+4 +4+1+1+1+1 +1+1)
val |= shift(cond_bit_code , 12+4 +4+1+1+1+1 +1+1+2)
io.write_uint32 val
end
def uses
ret = [@left.register ]
ret << @right.register unless @right.nil?
ret
end
def assigns
[@result.register]
end
end
end

112
lib/arm/instructions/move_instruction.rb Normal file
View File

@ -0,0 +1,112 @@
module Arm
class MoveInstruction < Register::Instruction
include Constants
include Attributed
def initialize to , from , options = {}
super(nil)
@attributes = options
if( from.is_a?(Symbol) and Register::RegisterValue.look_like_reg(from) )
from = Register::RegisterValue.new(from , :Integer)
end
@from = from
@to = to
raise "move must have from set #{inspect}" unless from
@attributes[:update_status] = 1 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@attributes[:opcode] = attributes[:opcode]
@operand = 0
@immediate = 0
@rn = :r0 # register zero = zero bit pattern
@extra = nil
end
attr_accessor :to , :from
# arm intructions are pretty sensible, and always 4 bytes (thumb not supported)
# but not all constants fit into the part of the instruction that is left after the instruction
# code, so large moves have to be split into two instructions.
# we handle this "transparently", just this instruction looks longer
# alas, full transparency is not achieved as we only know when to use 2 instruction once we
# know where the other object is, and that position is only set after code positions have been
# determined (in link) and so see below in assemble
def byte_length
@extra ? 8 : 4
end
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
rn = @rn
operand = @operand
immediate = @immediate
right = @from
if (right.is_a?(Numeric))
if (right.fits_u8?)
# no shifting needed
operand = right
immediate = 1
elsif (op_with_rot = calculate_u8_with_rr(right))
operand = op_with_rot
immediate = 1
else
# unfortunately i was wrong in thinking the pi is armv7. The good news is the code
# below implements the movw instruction (armv7 for moving a word) and works
#armv7 raise "Too big #{right} " if (right >> 16) > 0
#armv7 operand = (right & 0xFFF)
#armv7 immediate = 1
#armv7 rn = (right >> 12)
# a little STRANGE, that the armv7 movw (move a 2 byte word) is an old test opcode,
# but there it is
#armv7 @attributes[:opcode] = :tst
raise "No negatives implemented #{right} " if right < 0
# and so it continues: when we notice that the const doesn't fit, first time we raise an
# error,but set the extra flag, to say the instruction is now 8 bytes
# then on subsequent assemblies we can assemble
unless @extra
@extra = 1
#puts "RELINK M at #{self.position.to_s(16)}"
raise ::Register::LinkException.new("cannot fit numeric literal argument in operand #{right.inspect}")
end
# now we can do the actual breaking of instruction, by splitting the operand
first = right & 0xFFFFFF00
operand = calculate_u8_with_rr( first )
raise "no fit for #{right}" unless operand
immediate = 1
@extra = ArmMachine.add( to , to , (right & 0xFF) )
#TODO: this is still a hack, as it does not encode all possible values.
# The way it _should_ be done
# is to check that the first part is doabe with u8_with_rr AND leaves a u8 remainder
end
elsif( right.is_a? Register::RegisterValue)
operand = reg_code(right)
immediate = 0 # ie not immediate is register
else
raise "invalid operand argument #{right.class} , #{self.class}"
end
op = shift_handling
instuction_class = 0b00 # OPC_DATA_PROCESSING
val = shift(operand , 0)
val |= shift(op , 0) # any barrel action, is already shifted
val |= shift(reg_code(@to) , 12)
val |= shift(reg_code(rn) , 12+4)
val |= shift(@attributes[:update_status] , 12+4+4)#20
val |= shift(op_bit_code , 12+4+4 + 1)
val |= shift(immediate , 12+4+4 + 1+4)
val |= shift(instuction_class , 12+4+4 + 1+4+1)
val |= shift(cond_bit_code , 12+4+4 + 1+4+1+2)
io.write_uint32 val
# by now we have the extra add so assemble that
if(@extra)
@extra.assemble(io)
#puts "Assemble extra at #{val.to_s(16)}"
end
end
def uses
@from.is_a?(Constant) ? [] : [@from.register]
end
def assigns
[@to.register]
end
end
end

82
lib/arm/instructions/stack_instruction.rb Normal file
View File

@ -0,0 +1,82 @@
module Arm
# ADDRESSING MODE 4
class StackInstruction < Register::Instruction
include Constants
include Attributed
def initialize(first , attributes)
super(nil)
@attributes = attributes
@first = first
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
@attributes[:opcode] = attributes[:opcode]
@operand = 0
# @attributes[:update_status]= 0
@rn = :r0 # register zero = zero bit pattern
# downward growing, decrement before memory access
# official ARM style stack as used by gas
end
def assemble(io)
# don't overwrite instance variables, to make assembly repeatable
operand = @operand
if (@first.is_a?(Array))
operand = 0
@first.each do |r|
raise "nil register in push, index #{r}- #{inspect}" if r.nil?
operand = operand | (1 << reg_code(r))
end
else
raise "invalid operand argument #{inspect}"
end
write_base = 1
if (opcode == :push)
pre_post_index = 1
up_down = 0
is_pop = 0
else #pop
pre_post_index = 0
up_down = 1
is_pop = 1
end
instuction_class = 0b10 # OPC_STACK
cond = @attributes[:condition_code].is_a?(Symbol) ? COND_CODES[@attributes[:condition_code]] : @attributes[:condition_code]
@rn = :sp # sp register
#assemble of old
val = operand
val = val | (reg_code(@rn) << 16)
val = val | (is_pop << 16+4) #20
val = val | (write_base << 16+4+ 1)
val = val | (@attributes[:update_status] << 16+4+ 1+1)
val = val | (up_down << 16+4+ 1+1+1)
val = val | (pre_post_index << 16+4+ 1+1+1+1)#24
val = val | (instuction_class << 16+4+ 1+1+1+1 +2)
val = val | (cond << 16+4+ 1+1+1+1 +2+2)
io.write_uint32 val
end
def is_push?
opcode == :push
end
def is_pop?
!is_push?
end
def uses
is_push? ? regs : []
end
def assigns
is_pop? ? regs : []
end
def regs
@first
end
def to_s
"#{opcode} [#{@first.join(',') }] #{super}"
end
end
end

81
lib/arm/machine_code.rb Normal file
View File

@ -0,0 +1,81 @@
module Arm
class MachineCode
def function_call into , call
raise "Not CallSite #{call.inspect}" unless call.is_a? Register::CallSite
raise "Not linked #{call.inspect}" unless call.function
into.add_code call( call.function )
raise "No return type for #{call.function.name}" unless call.function.return_type
call.function.return_type
end
def main_start context
entry = Register::Block.new("main_entry",nil,nil)
entry.add_code mov( :fp , 0 )
entry.add_code call( context.function )
entry
end
def main_exit context
exit = Register::Block.new("main_exit",nil,nil)
syscall(exit , 1)
exit
end
def function_entry block, f_name
block.add_code push( [:lr] )
block
end
def function_exit entry , f_name
entry.add_code pop( [:pc] )
entry
end
# assumes string in standard receiver reg (r2) and moves them down for the syscall
def write_stdout function #, string
# TODO save and restore r0
function.mov( :r0 , 1 ) # 1 == stdout
function.mov( :r1 , receiver_register )
function.mov( receiver_register , :r3 )
syscall( function.insertion_point , 4 ) # 4 == write
end
# stop, do not return
def exit function #, string
syscall( function.insertion_point , 1 ) # 1 == exit
end
# the number (a Register::integer) is (itself) divided by 10, ie overwritten by the result
# and the remainder is overwritten (ie an out argument)
# not really a function, more a macro,
def div10 function, number , remainder
# Note about division: devision is MUCH more expensive than one would have thought
# And coding it is a bit of a mind leap: it's all about finding a a result that gets the
# remainder smaller than an int. i'll post some links sometime. This is from the arm manual
tmp = function.new_local
function.instance_eval do
sub( remainder , number , 10 )
sub( number , number , number , shift_lsr: 2)
add( number , number , number , shift_lsr: 4)
add( number , number , number , shift_lsr: 8)
add( number , number , number , shift_lsr: 16)
mov( number , number , shift_lsr: 3)
add( tmp , number , number , shift_lsl: 2)
sub( remainder , remainder , tmp , shift_lsl: 1 , update_status: 1)
add( number , number, 1 , condition_code: :pl )
add( remainder , remainder , 10 , condition_code: :mi )
end
end
def syscall block , num
# This is very arm specific, syscall number is passed in r7,
# other arguments like a c call ie 0 and up
sys = Register::Integer.new( Register::RegisterValue.new(SYSCALL_REG) )
ret = Register::Integer.new( Register::RegisterValue.new(RETURN_REG) )
block.add_code mov( sys , num )
block.add_code swi( 0 )
#todo should write type into r1 according to syscall
ret
end
end
end