folded salama-arm in
This commit is contained in:
Torsten Ruger
parent
56032c9b08
commit
456e9b1ec0
2
Gemfile
2
Gemfile
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@ -8,8 +8,6 @@ gem "rye"
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gem "salama-object-file" , :github => "salama/salama-object-file"
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#gem "salama-object-file" , :path => "../salama-object-file"
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gem "salama-arm" , :github => "salama/salama-arm"
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#gem "salama-arm" , :path => "../salama-arm"
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gem "codeclimate-test-reporter", require: nil
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@ -1,9 +1,3 @@
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GIT
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remote: git://github.com/salama/salama-arm.git
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revision: 866ae7ad961f1a387bfb75526fa170006005b13f
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specs:
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salama-arm (0.5.0)
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GIT
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remote: git://github.com/salama/salama-object-file.git
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revision: aab01b23108f10063433b1ef9f703ff2927d0b80
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@ -112,7 +106,6 @@ DEPENDENCIES
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rb-readline
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rye
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salama!
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salama-arm!
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salama-object-file!
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BUNDLED WITH
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@ -0,0 +1,113 @@
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require_relative "attributed"
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module Arm
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# A Machines main responsibility in the framework is to instantiate Instructions
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# Value functions are mapped to machines by concatenating the values class name + the methd name
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# Example: IntegerValue.plus( value ) -> Machine.signed_plus (value )
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# Also, shortcuts are created to easily instantiate Instruction objects.
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# Example: pop -> StackInstruction.new( {:opcode => :pop}.merge(options) )
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# Instructions work with options, so you can pass anything in, and the only thing the functions
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# does is save you typing the clazz.new. It passes the function name as the :opcode
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class ArmMachine
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# conditions specify all the possibilities for branches. Branches are b + condition
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# Example: beq means brach if equal.
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# :al means always, so bal is an unconditional branch (but b() also works)
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CONDITIONS = [:al ,:eq ,:ne ,:lt ,:le ,:ge,:gt ,:cs ,:mi ,:hi ,:cc ,:pl,:ls ,:vc ,:vs]
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# here we create the shortcuts for the "standard" instructions, see above
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# Derived machines may use own instructions and define functions for them if so desired
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def self.init
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[:push, :pop].each do |inst|
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define_instruction_one(inst , StackInstruction)
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end
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[:adc, :add, :and, :bic, :eor, :orr, :rsb, :rsc, :sbc, :sub , :mul].each do |inst|
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define_instruction_three(inst , LogicInstruction)
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end
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[:mov, :mvn].each do |inst|
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define_instruction_two(inst , MoveInstruction)
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end
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[:cmn, :cmp, :teq, :tst].each do |inst|
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define_instruction_two(inst , CompareInstruction)
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end
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[:strb, :str , :ldrb, :ldr].each do |inst|
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define_instruction_three(inst , MemoryInstruction)
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end
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[:b, :call , :swi].each do |inst|
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define_instruction_one(inst , CallInstruction)
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end
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# create all possible brach instructions, but the CallInstruction demangles the
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# code, and has opcode set to :b and :condition_code set to the condition
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CONDITIONS.each do |suffix|
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define_instruction_one("b#{suffix}".to_sym , CallInstruction)
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define_instruction_one("call#{suffix}".to_sym , CallInstruction)
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end
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end
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def self.create_method(name, &block)
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self.class.send(:define_method, name , &block)
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end
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def self.class_for clazz
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my_module = self.class.name.split("::").first
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clazz_name = clazz.name.split("::").last
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if(my_module != Register )
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module_class = eval("#{my_module}::#{clazz_name}") rescue nil
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clazz = module_class if module_class
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end
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clazz
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end
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#defining the instruction (opcode, symbol) as an given class.
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# the class is a Register::Instruction derived base class and to create machine specific function
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# an actual machine must create derived classes (from this base class)
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# These instruction classes must follow a naming pattern and take a hash in the contructor
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# Example, a mov() opcode instantiates a Register::MoveInstruction
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# for an Arm machine, a class Arm::MoveInstruction < Register::MoveInstruction exists, and it
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# will be used to define the mov on an arm machine.
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# This methods picks up that derived class and calls a define_instruction methods that can
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# be overriden in subclasses
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def self.define_instruction_one(inst , clazz , defaults = {} )
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clazz = class_for(clazz)
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create_method(inst) do |first , options = nil|
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options = {} if options == nil
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options.merge defaults
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options[:opcode] = inst
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first = Register::RegisterValue.convert(first)
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clazz.new(first , options)
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end
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end
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# same for two args (left right, from to etc)
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def self.define_instruction_two(inst , clazz , defaults = {} )
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clazz = self.class_for(clazz)
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create_method(inst) do |left ,right , options = nil|
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options = {} if options == nil
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options.merge defaults
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left = Register::RegisterValue.convert(left)
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right = Register::RegisterValue.convert(right)
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options[:opcode] = inst
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clazz.new(left , right ,options)
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end
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end
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# same for three args (result = left right,)
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def self.define_instruction_three(inst , clazz , defaults = {} )
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clazz = self.class_for(clazz)
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create_method(inst) do |result , left ,right = nil , options = nil|
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options = {} if options == nil
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options.merge defaults
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options[:opcode] = inst
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result = Register::RegisterValue.convert(result)
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left = Register::RegisterValue.convert(left)
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right = Register::RegisterValue.convert(right)
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clazz.new(result, left , right ,options)
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end
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end
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end
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end
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Arm::ArmMachine.init
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@ -0,0 +1,38 @@
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module Arm
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# The arm machine has following instruction classes
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# - Memory
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# - Stack
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# - Logic
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# - Math
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# - Control/Compare
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# - Move
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# - Call class Instruction
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module Attributed
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attr_reader :attributes
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def opcode
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@attributes[:opcode]
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end
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def set_opcode code
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@attributes[:opcode] = code
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end
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# for the shift handling that makes the arm so unique
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def shift val , by
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raise "Not integer #{val}:#{val.class} #{inspect}" unless val.is_a? Fixnum
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val << by
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end
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def byte_length
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4
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end
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end
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end
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require_relative "constants"
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require_relative "instructions/call_instruction"
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require_relative "instructions/compare_instruction"
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require_relative "instructions/logic_instruction"
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require_relative "instructions/memory_instruction"
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require_relative "instructions/move_instruction"
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require_relative "instructions/stack_instruction"
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@ -0,0 +1,135 @@
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module Arm
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module Constants
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OPCODES = {
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:adc => 0b0101, :add => 0b0100,
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:and => 0b0000, :bic => 0b1110,
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:eor => 0b0001, :orr => 0b1100,
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:rsb => 0b0011, :rsc => 0b0111,
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:sbc => 0b0110, :sub => 0b0010,
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:mul => 0b0000 , # reverse engineered, shoud check
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# for these Rn is sbz (should be zero)
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:mov => 0b1101,
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:mvn => 0b1111,
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# for these Rd is sbz and S=1
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:cmn => 0b1011,
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:cmp => 0b1010,
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:teq => 0b1001,
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:tst => 0b1000,
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:b => 0b1010,
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:call=> 0b1011
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}
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#return the bit patter that the cpu uses for the current instruction @attributes[:opcode]
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def op_bit_code
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bit_code = OPCODES[opcode]
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bit_code or raise "no code found for #{opcode} #{inspect}"
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end
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#codition codes can be applied to many instructions and thus save branches
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# :al => always , :eq => equal and so on
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# eq mov if equal :moveq r1 r2 (also exists as function) will only execute
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# if the last operation was 0
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COND_CODES = {
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:al => 0b1110, :eq => 0b0000,
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:ne => 0b0001, :cs => 0b0010,
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:mi => 0b0100, :hi => 0b1000,
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:cc => 0b0011, :pl => 0b0101,
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:ls => 0b1001, :vc => 0b0111,
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:lt => 0b1011, :le => 0b1101,
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:ge => 0b1010, :gt => 0b1100,
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:vs => 0b0110
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}
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# return the bit pattern for the @attributes[:condition_code] variable,
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# which signals the conditional code
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def cond_bit_code
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COND_CODES[@attributes[:condition_code]] or throw "no code found for #{@attributes[:condition_code]}"
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end
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REGISTERS = { 'r0' => 0, 'r1' => 1, 'r2' => 2, 'r3' => 3, 'r4' => 4, 'r5' => 5,
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'r6' => 6, 'r7' => 7, 'r8' => 8, 'r9' => 9, 'r10' => 10, 'r11' => 11,
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'r12' => 12, 'r13' => 13, 'r14' => 14, 'r15' => 15, 'a1' => 0, 'a2' => 1,
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'a3' => 2, 'a4' => 3, 'v1' => 4, 'v2' => 5, 'v3' => 6, 'v4' => 7, 'v5' => 8,
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'v6' => 9, 'rfp' => 9, 'sl' => 10, 'fp' => 11, 'ip' => 12, 'sp' => 13,
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'lr' => 14, 'pc' => 15 }
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def reg r_name
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code = reg_code r_name
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raise "no such register #{r_name}" unless code
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Arm::Register.new(r_name.to_sym , code )
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end
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def reg_code r_name
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raise "double r #{r_name}" if( :rr1 == r_name)
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if r_name.is_a? ::Register::RegisterValue
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r_name = r_name.symbol
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end
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if r_name.is_a? Fixnum
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r_name = "r#{r_name}"
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end
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r = REGISTERS[r_name.to_s]
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raise "no reg #{r_name}" if r == nil
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r
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end
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def calculate_u8_with_rr(arg)
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parts = arg.to_s(2).rjust(32,'0').scan(/^(0*)(.+?)0*$/).flatten
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pre_zeros = parts[0].length
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imm_len = parts[1].length
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if ((pre_zeros+imm_len) % 2 == 1)
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u8_imm = (parts[1]+'0').to_i(2)
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imm_len += 1
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else
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u8_imm = parts[1].to_i(2)
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end
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if u8_imm.fits_u8?
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# can do!
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rot_imm = (pre_zeros+imm_len) / 2
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if (rot_imm > 15)
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return nil
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end
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return u8_imm | (rot_imm << 8)
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else
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return nil
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end
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end
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Register::RegisterValue.class_eval do
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def reg_no
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@symbol.to_s[1 .. -1].to_i
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end
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end
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#slighly wrong place for this code, but since the module gets included in instructions anyway . . .
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# implement the barrel shifter on the operand (which is set up before as an integer)
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def shift_handling
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op = 0
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#codes that one can shift, first two probably most common.
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# l (in lsr) means logical, ie unsigned, a (in asr) is arithmetic, ie signed
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shift_codes = {'lsl' => 0b000, 'lsr' => 0b010, 'asr' => 0b100, 'ror' => 0b110, 'rrx' => 0b110}
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shift_codes.each do |short, bin|
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long = "shift_#{short}".to_sym
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if shif = @attributes[long]
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# TODO need more tests
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if (shif.is_a?(Numeric))
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raise "0 < shift <= 32 #{shif} #{inspect}" if (shif >= 32) or( shif < 0)
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op |= shift(bin , 4 )
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op |= shift(shif , 4+3)
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else
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bin |= 0x1;
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op |= shift(bin , 4 )
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op |= shift(shif.reg_no , 8)
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end
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break
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end
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end
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return op
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end
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# arm intrucioons are pretty sensible, and always 4 bytes (thumb not supported)
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def byte_length
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4
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end
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end
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end
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@ -0,0 +1,94 @@
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module Arm
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# There are only three call instructions in arm branch (b), call (bl) and syscall (swi)
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# A branch could be called a jump as it has no notion of returning
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# The pc is put into the link register to make a return possible
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# a return is affected by moving the stored link register into the pc, effectively a branch
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# swi (SoftWareInterrupt) or system call is how we call the kernel.
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# in Arm the register layout is different and so we have to place the syscall code into register 7
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# Registers 0-6 hold the call values as for a normal c call
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class CallInstruction < Register::Branch
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include Constants
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include Attributed
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def initialize(first, attributes)
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super(nil, nil)
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@attributes = attributes
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raise "no target" if first.nil?
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@first = first
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opcode = @attributes[:opcode].to_s
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if opcode.length == 3 and opcode[0] == "b"
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@attributes[:condition_code] = opcode[1,2].to_sym
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@attributes[:opcode] = :b
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end
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if opcode.length == 6 and opcode[0] == "c"
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@attributes[:condition_code] = opcode[4,2].to_sym
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@attributes[:opcode] = :call
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end
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@attributes[:update_status] = 0
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@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
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end
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def assemble(io)
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case @attributes[:opcode]
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when :b, :call
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arg = @first
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if arg.is_a?(Register::Label) or arg.is_a?(Parfait::TypedMethod)
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#relative addressing for jumps/calls
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# but because of the arm "theoretical" 3- stage pipeline,
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# we have to subtract 2 words (fetch/decode)
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if(arg.is_a? Register::Label)
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diff = arg.position - self.position - 8
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else
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# But, for methods, this happens to be the size of the object header,
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# so there it balances out, but not blocks
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# have to use the code, not the mthod object for methods
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diff = arg.binary.position - self.position
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end
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arg = diff
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end
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if (arg.is_a?(Numeric))
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jmp_val = arg >> 2
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packed = [jmp_val].pack('l')
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# signed 32-bit, condense to 24-bit
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# TODO add check that the value fits into 24 bits
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io << packed[0,3]
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else
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raise "else not Attributed arg =\n#{arg.to_s[0..1000]}: #{inspect[0..1000]}"
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end
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io.write_uint8 op_bit_code | (COND_CODES[@attributes[:condition_code]] << 4)
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when :swi
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arg = @first
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if (arg.is_a?(Numeric))
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packed = [arg].pack('L')[0,3]
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io << packed
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io.write_uint8 0b1111 | (COND_CODES[@attributes[:condition_code]] << 4)
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else
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raise "invalid operand argument expected literal not #{arg} #{inspect}"
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end
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else
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raise "Should not be the case #{inspect}"
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end
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end
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def uses
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if opcode == :call
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@first.args.collect {|arg| arg.register }
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else
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[]
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end
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end
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def assigns
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if opcode == :call
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[RegisterValue.new(RegisterMachine.instance.return_register)]
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else
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[]
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end
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end
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def to_s
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"#{opcode} #{@first} #{super}"
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end
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end
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end
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@ -0,0 +1,103 @@
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module Arm
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class CompareInstruction < Register::Instruction
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include Constants
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include Attributed
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def initialize(left , right , attributes)
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super(nil)
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@attributes = attributes
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@left = left
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@right = right.is_a?(Fixnum) ? IntegerConstant.new(right) : right
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@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
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@operand = 0
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@immediate = 0
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@attributes[:update_status] = 1
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@rn = left
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@rd = :r0
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end
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def assemble(io)
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# don't overwrite instance variables, to make assembly repeatable
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rn = @rn
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operand = @operand
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immediate = @immediate
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arg = @right
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if arg.is_a?(Parfait::Object)
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# do pc relative addressing with the difference to the instuction
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# 8 is for the funny pipeline adjustment (ie oc pointing to fetch and not execute)
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arg = arg.position - self.position - 8
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rn = :pc
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end
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if( arg.is_a? Symbol )
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arg = Register::RegisterValue.new( arg , :Integer)
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end
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if (arg.is_a?(Numeric))
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if (arg.fits_u8?)
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# no shifting needed
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operand = arg
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immediate = 1
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elsif (op_with_rot = calculate_u8_with_rr(arg))
|
||||
operand = op_with_rot
|
||||
immediate = 1
|
||||
raise "hmm"
|
||||
else
|
||||
raise "cannot fit numeric literal argument in operand #{arg.inspect}"
|
||||
end
|
||||
elsif (arg.is_a?(Symbol) or arg.is_a?(::Register::RegisterValue))
|
||||
operand = arg
|
||||
immediate = 0
|
||||
elsif (arg.is_a?(Arm::Shift))
|
||||
rm_ref = arg.argument
|
||||
immediate = 0
|
||||
shift_op = {'lsl' => 0b000, 'lsr' => 0b010, 'asr' => 0b100,
|
||||
'ror' => 0b110, 'rrx' => 0b110}[arg.type]
|
||||
if (arg.type == 'ror' and arg.value.nil?)
|
||||
# ror #0 == rrx
|
||||
raise "cannot rotate by zero #{arg} #{inspect}"
|
||||
end
|
||||
|
||||
arg1 = arg.value
|
||||
if (arg1.is_a?(Register::IntegerConstant))
|
||||
if (arg1.value >= 32)
|
||||
raise "cannot shift by more than 31 #{arg1} #{inspect}"
|
||||
end
|
||||
shift_imm = arg1.value
|
||||
elsif (arg1.is_a?(Arm::Register))
|
||||
shift_op val |= 0x1;
|
||||
shift_imm = arg1.number << 1
|
||||
elsif (arg.type == 'rrx')
|
||||
shift_imm = 0
|
||||
end
|
||||
operand = rm_ref | (shift_op << 4) | (shift_imm << 4+3)
|
||||
else
|
||||
raise "invalid operand argument #{arg.inspect} , #{inspect}"
|
||||
end
|
||||
instuction_class = 0b00 # OPC_DATA_PROCESSING
|
||||
val = (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterValue)) ? reg_code(operand) : operand
|
||||
val = 0 if val == nil
|
||||
val = shift(val , 0)
|
||||
raise inspect unless reg_code(@rd)
|
||||
val |= shift(reg_code(@rd) , 12)
|
||||
val |= shift(reg_code(rn) , 12+4)
|
||||
val |= shift(@attributes[:update_status] , 12+4+4)#20
|
||||
val |= shift(op_bit_code , 12+4+4 +1)
|
||||
val |= shift(immediate , 12+4+4 +1+4)
|
||||
val |= shift(instuction_class , 12+4+4 +1+4+1)
|
||||
val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
|
||||
io.write_uint32 val
|
||||
end
|
||||
|
||||
def uses
|
||||
ret = [@left.register ]
|
||||
ret << @right.register unless @right.is_a? Constant
|
||||
ret
|
||||
end
|
||||
def assigns
|
||||
[]
|
||||
end
|
||||
def to_s
|
||||
"#{opcode} #{@left} , #{@right} #{super}"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
module Arm
|
||||
class LogicInstruction < Register::Instruction
|
||||
include Constants
|
||||
include Attributed
|
||||
|
||||
# result = left op right
|
||||
#
|
||||
# Logic instruction are your basic operator implementation. But unlike the (normal) code we write
|
||||
# these Instructions must have "place" to write their results. Ie when you write 4 + 5 in ruby
|
||||
# the result is sort of up in the air, but with Instructions the result must be assigned
|
||||
def initialize(result , left , right , attributes = {})
|
||||
super(nil)
|
||||
@attributes = attributes
|
||||
@result = result
|
||||
@left = left
|
||||
@right = right
|
||||
@attributes[:update_status] = 1 if @attributes[:update_status] == nil
|
||||
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
|
||||
@operand = 0
|
||||
|
||||
raise "Left arg must be given #{inspect}" unless @left
|
||||
@immediate = 0
|
||||
end
|
||||
|
||||
attr_accessor :result , :left , :right
|
||||
def assemble(io)
|
||||
# don't overwrite instance variables, to make assembly repeatable
|
||||
left = @left
|
||||
operand = @operand
|
||||
immediate = @immediate
|
||||
|
||||
right = @right
|
||||
if( @left.is_a?(Parfait::Object) or @left.is_a?(Register::Label) or
|
||||
(@left.is_a?(Symbol) and !Register::RegisterValue.look_like_reg(@left)))
|
||||
# do pc relative addressing with the difference to the instuction
|
||||
# 8 is for the funny pipeline adjustment (ie pointing to fetch and not execute)
|
||||
right = @left.position - self.position - 8
|
||||
if( (right < 0) && ((opcode == :add) || (opcode == :sub)) )
|
||||
right *= -1 # this works as we never issue sub only add
|
||||
set_opcode :sub # so (as we can't change the sign permanently) we can change the opcode
|
||||
end # and the sign even for sub (becuase we created them)
|
||||
raise "No negatives implemented #{self} #{right} " if right < 0
|
||||
left = :pc
|
||||
end
|
||||
if (right.is_a?(Numeric))
|
||||
if (right.fits_u8?)
|
||||
# no shifting needed
|
||||
operand = right
|
||||
immediate = 1
|
||||
elsif (op_with_rot = calculate_u8_with_rr(right))
|
||||
operand = op_with_rot
|
||||
immediate = 1
|
||||
else
|
||||
#TODO this is copied from MoveInstruction, should rework
|
||||
unless @extra
|
||||
@extra = 1
|
||||
#puts "RELINK L at #{self.position.to_s(16)}"
|
||||
raise ::Register::LinkException.new("cannot fit numeric literal argument in operand #{right.inspect}")
|
||||
end
|
||||
# now we can do the actual breaking of instruction, by splitting the operand
|
||||
first = right & 0xFFFFFF00
|
||||
operand = calculate_u8_with_rr( first )
|
||||
raise "no fit for #{right}" unless operand
|
||||
immediate = 1
|
||||
# use sub for sub and add for add, ie same as opcode
|
||||
@extra = ArmMachine.send( opcode , result , result , (right & 0xFF) )
|
||||
end
|
||||
elsif (right.is_a?(Symbol) or right.is_a?(::Register::RegisterValue))
|
||||
operand = reg_code(right) #integer means the register the integer is in (otherwise constant)
|
||||
immediate = 0 # ie not immediate is register
|
||||
else
|
||||
raise "invalid operand argument #{right.inspect} , #{inspect}"
|
||||
end
|
||||
result = reg_code(@result)
|
||||
left_code = reg_code(left)
|
||||
op = shift_handling
|
||||
instuction_class = 0b00 # OPC_DATA_PROCESSING
|
||||
if( opcode == :mul )
|
||||
operand = reg_code(left) + 0x90
|
||||
op = reg_code(right) << 8
|
||||
result = 0
|
||||
left_code = reg_code(@result)
|
||||
end
|
||||
val = shift(operand , 0)
|
||||
val |= shift(op , 0) # any barrel action, is already shifted
|
||||
val |= shift(result , 12)
|
||||
val |= shift(left_code , 12+4)
|
||||
val |= shift(@attributes[:update_status] , 12+4+4)#20
|
||||
val |= shift(op_bit_code , 12+4+4 + 1)
|
||||
val |= shift(immediate , 12+4+4 + 1+4)
|
||||
val |= shift(instuction_class , 12+4+4 + 1+4+1)
|
||||
val |= shift(cond_bit_code , 12+4+4 + 1+4+1+2)
|
||||
io.write_uint32 val
|
||||
# by now we have the extra add so assemble that
|
||||
if(@extra)
|
||||
if(@extra == 1) # unles things have changed and then we add a noop (to keep the length same)
|
||||
@extra = ArmMachine.mov( :r1 , :r1 )
|
||||
end
|
||||
@extra.assemble(io)
|
||||
#puts "Assemble extra at #{val.to_s(16)}"
|
||||
end
|
||||
end
|
||||
|
||||
def byte_length
|
||||
@extra ? 8 : 4
|
||||
end
|
||||
|
||||
def to_s
|
||||
"#{self.class.name} #{opcode} #{@result} = #{@left} #{@right} extra=#{@extra}"
|
||||
end
|
||||
def uses
|
||||
ret = []
|
||||
ret << @left.register if @left and not @left.is_a? Constant
|
||||
ret << @right.register if @right and not @right.is_a?(Constant)
|
||||
ret
|
||||
end
|
||||
def assigns
|
||||
[@result.register]
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
module Arm
|
||||
# ADDRESSING MODE 2
|
||||
# Implemented: immediate offset with offset=0
|
||||
|
||||
class MemoryInstruction < Register::Instruction
|
||||
include Constants
|
||||
include Attributed
|
||||
|
||||
def initialize result , left , right = nil , attributes = {}
|
||||
super(nil)
|
||||
@attributes = attributes
|
||||
@result = result
|
||||
@left = left
|
||||
@right = right
|
||||
@attributes[:update_status] = 1 if @attributes[:update_status] == nil
|
||||
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
|
||||
@operand = 0
|
||||
raise "alert" if right.is_a? Register::Label
|
||||
@pre_post_index = 0 #P flag
|
||||
@add_offset = 0 #U flag
|
||||
@is_load = opcode.to_s[0] == "l" ? 1 : 0 #L (load) flag
|
||||
end
|
||||
|
||||
def assemble(io)
|
||||
# don't overwrite instance variables, to make assembly repeatable
|
||||
rn = @rn
|
||||
operand = @operand
|
||||
add_offset = @add_offset
|
||||
arg = @left
|
||||
arg = arg.symbol if( arg.is_a? ::Register::RegisterValue )
|
||||
#str / ldr are _serious instructions. With BIG possibilities not half are implemented
|
||||
is_reg = arg.is_a?(::Register::RegisterValue)
|
||||
if( arg.is_a?(Symbol) and not is_reg)
|
||||
is_reg = (arg.to_s[0] == "r")
|
||||
end
|
||||
if (is_reg ) #symbol is register
|
||||
rn = arg
|
||||
if @right
|
||||
operand = @right
|
||||
#TODO better test, this operand integer (register) does not work. but sleep first
|
||||
operand = operand.symbol if operand.is_a? ::Register::RegisterValue
|
||||
unless( operand.is_a? Symbol)
|
||||
#puts "operand #{operand.inspect}"
|
||||
if (operand < 0)
|
||||
add_offset = 0
|
||||
#TODO test/check/understand
|
||||
operand *= -1
|
||||
else
|
||||
add_offset = 1
|
||||
end
|
||||
if (@operand.abs > 4095)
|
||||
raise "reference offset too large/small (max 4095) #{arg} #{inspect}"
|
||||
end
|
||||
end
|
||||
end
|
||||
elsif (arg.is_a?(Parfait::Object) or arg.is_a? Symbol ) #use pc relative
|
||||
rn = :pc
|
||||
operand = arg.position - self.position - 8 #stringtable is after code
|
||||
add_offset = 1
|
||||
if (operand.abs > 4095)
|
||||
raise "reference offset too large/small (4095<#{operand}) #{arg} #{inspect}"
|
||||
end
|
||||
elsif( arg.is_a?(Numeric) )
|
||||
#TODO untested branch, probably not working
|
||||
raise "is this working ?? #{arg} #{inspect}"
|
||||
@pre_post_index = 1
|
||||
@rn = pc
|
||||
@use_addrtable_reloc = true
|
||||
@addrtable_reloc_target = arg
|
||||
else
|
||||
raise "invalid operand argument #{arg.inspect} #{inspect}"
|
||||
end
|
||||
#not sure about these 2 constants. They produce the correct output for str r0 , r1
|
||||
# but i can't help thinking that that is because they are not used in that instruction and
|
||||
# so it doesn't matter. Will see
|
||||
add_offset = 1
|
||||
# TODO to be continued
|
||||
add_offset = 0 if @attributes[:add_offset]
|
||||
@pre_post_index = 1
|
||||
@pre_post_index = 0 if @attributes[:pre_post_index]
|
||||
w = 0 #W flag
|
||||
byte_access = opcode.to_s[-1] == "b" ? 1 : 0 #B (byte) flag
|
||||
instuction_class = 0b01 # OPC_MEMORY_ACCESS
|
||||
if (operand.is_a?(Symbol) or operand.is_a?(::Register::RegisterValue))
|
||||
val = reg_code(operand)
|
||||
@pre_post_index = 0
|
||||
i = 1 # not quite sure about this, but it gives the output of as. read read read.
|
||||
else
|
||||
i = 0 #I flag (third bit)
|
||||
val = operand
|
||||
end
|
||||
# testing against gnu as, setting the flag produces correct output
|
||||
# but gnu as produces same output for auto_inc or not, so that seems broken
|
||||
# luckily auto_inc is not used and even if it clobbers unused reg in soml, but still
|
||||
@pre_post_index = 1
|
||||
op = shift_handling
|
||||
val = shift(val , 0 ) # for the test
|
||||
val |= shift(op , 0)
|
||||
val |= shift(reg_code(@result) , 12 )
|
||||
val |= shift(reg_code(rn) , 12+4) #16
|
||||
val |= shift(@is_load , 12+4 +4)
|
||||
val |= shift(w , 12+4 +4+1)
|
||||
val |= shift(byte_access , 12+4 +4+1+1)
|
||||
val |= shift(add_offset , 12+4 +4+1+1+1)
|
||||
val |= shift(@pre_post_index, 12+4 +4+1+1+1+1)#24
|
||||
val |= shift(i , 12+4 +4+1+1+1+1 +1)
|
||||
val |= shift(instuction_class,12+4 +4+1+1+1+1 +1+1)
|
||||
val |= shift(cond_bit_code , 12+4 +4+1+1+1+1 +1+1+2)
|
||||
io.write_uint32 val
|
||||
end
|
||||
|
||||
def uses
|
||||
ret = [@left.register ]
|
||||
ret << @right.register unless @right.nil?
|
||||
ret
|
||||
end
|
||||
def assigns
|
||||
[@result.register]
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
module Arm
|
||||
class MoveInstruction < Register::Instruction
|
||||
include Constants
|
||||
include Attributed
|
||||
|
||||
def initialize to , from , options = {}
|
||||
super(nil)
|
||||
@attributes = options
|
||||
if( from.is_a?(Symbol) and Register::RegisterValue.look_like_reg(from) )
|
||||
from = Register::RegisterValue.new(from , :Integer)
|
||||
end
|
||||
@from = from
|
||||
@to = to
|
||||
raise "move must have from set #{inspect}" unless from
|
||||
@attributes[:update_status] = 1 if @attributes[:update_status] == nil
|
||||
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
|
||||
@attributes[:opcode] = attributes[:opcode]
|
||||
@operand = 0
|
||||
|
||||
@immediate = 0
|
||||
@rn = :r0 # register zero = zero bit pattern
|
||||
@extra = nil
|
||||
end
|
||||
attr_accessor :to , :from
|
||||
|
||||
# arm intructions are pretty sensible, and always 4 bytes (thumb not supported)
|
||||
# but not all constants fit into the part of the instruction that is left after the instruction
|
||||
# code, so large moves have to be split into two instructions.
|
||||
# we handle this "transparently", just this instruction looks longer
|
||||
# alas, full transparency is not achieved as we only know when to use 2 instruction once we
|
||||
# know where the other object is, and that position is only set after code positions have been
|
||||
# determined (in link) and so see below in assemble
|
||||
def byte_length
|
||||
@extra ? 8 : 4
|
||||
end
|
||||
|
||||
def assemble(io)
|
||||
# don't overwrite instance variables, to make assembly repeatable
|
||||
rn = @rn
|
||||
operand = @operand
|
||||
immediate = @immediate
|
||||
right = @from
|
||||
if (right.is_a?(Numeric))
|
||||
if (right.fits_u8?)
|
||||
# no shifting needed
|
||||
operand = right
|
||||
immediate = 1
|
||||
elsif (op_with_rot = calculate_u8_with_rr(right))
|
||||
operand = op_with_rot
|
||||
immediate = 1
|
||||
else
|
||||
# unfortunately i was wrong in thinking the pi is armv7. The good news is the code
|
||||
# below implements the movw instruction (armv7 for moving a word) and works
|
||||
#armv7 raise "Too big #{right} " if (right >> 16) > 0
|
||||
#armv7 operand = (right & 0xFFF)
|
||||
#armv7 immediate = 1
|
||||
#armv7 rn = (right >> 12)
|
||||
# a little STRANGE, that the armv7 movw (move a 2 byte word) is an old test opcode,
|
||||
# but there it is
|
||||
#armv7 @attributes[:opcode] = :tst
|
||||
raise "No negatives implemented #{right} " if right < 0
|
||||
# and so it continues: when we notice that the const doesn't fit, first time we raise an
|
||||
# error,but set the extra flag, to say the instruction is now 8 bytes
|
||||
# then on subsequent assemblies we can assemble
|
||||
unless @extra
|
||||
@extra = 1
|
||||
#puts "RELINK M at #{self.position.to_s(16)}"
|
||||
raise ::Register::LinkException.new("cannot fit numeric literal argument in operand #{right.inspect}")
|
||||
end
|
||||
# now we can do the actual breaking of instruction, by splitting the operand
|
||||
first = right & 0xFFFFFF00
|
||||
operand = calculate_u8_with_rr( first )
|
||||
raise "no fit for #{right}" unless operand
|
||||
immediate = 1
|
||||
@extra = ArmMachine.add( to , to , (right & 0xFF) )
|
||||
#TODO: this is still a hack, as it does not encode all possible values.
|
||||
# The way it _should_ be done
|
||||
# is to check that the first part is doabe with u8_with_rr AND leaves a u8 remainder
|
||||
end
|
||||
elsif( right.is_a? Register::RegisterValue)
|
||||
operand = reg_code(right)
|
||||
immediate = 0 # ie not immediate is register
|
||||
else
|
||||
raise "invalid operand argument #{right.class} , #{self.class}"
|
||||
end
|
||||
op = shift_handling
|
||||
instuction_class = 0b00 # OPC_DATA_PROCESSING
|
||||
val = shift(operand , 0)
|
||||
val |= shift(op , 0) # any barrel action, is already shifted
|
||||
val |= shift(reg_code(@to) , 12)
|
||||
val |= shift(reg_code(rn) , 12+4)
|
||||
val |= shift(@attributes[:update_status] , 12+4+4)#20
|
||||
val |= shift(op_bit_code , 12+4+4 + 1)
|
||||
val |= shift(immediate , 12+4+4 + 1+4)
|
||||
val |= shift(instuction_class , 12+4+4 + 1+4+1)
|
||||
val |= shift(cond_bit_code , 12+4+4 + 1+4+1+2)
|
||||
io.write_uint32 val
|
||||
# by now we have the extra add so assemble that
|
||||
if(@extra)
|
||||
@extra.assemble(io)
|
||||
#puts "Assemble extra at #{val.to_s(16)}"
|
||||
end
|
||||
end
|
||||
|
||||
def uses
|
||||
@from.is_a?(Constant) ? [] : [@from.register]
|
||||
end
|
||||
def assigns
|
||||
[@to.register]
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
module Arm
|
||||
# ADDRESSING MODE 4
|
||||
|
||||
class StackInstruction < Register::Instruction
|
||||
include Constants
|
||||
include Attributed
|
||||
|
||||
def initialize(first , attributes)
|
||||
super(nil)
|
||||
@attributes = attributes
|
||||
@first = first
|
||||
@attributes[:update_status] = 0 if @attributes[:update_status] == nil
|
||||
@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
|
||||
@attributes[:opcode] = attributes[:opcode]
|
||||
@operand = 0
|
||||
|
||||
# @attributes[:update_status]= 0
|
||||
@rn = :r0 # register zero = zero bit pattern
|
||||
# downward growing, decrement before memory access
|
||||
# official ARM style stack as used by gas
|
||||
end
|
||||
|
||||
def assemble(io)
|
||||
# don't overwrite instance variables, to make assembly repeatable
|
||||
operand = @operand
|
||||
|
||||
if (@first.is_a?(Array))
|
||||
operand = 0
|
||||
@first.each do |r|
|
||||
raise "nil register in push, index #{r}- #{inspect}" if r.nil?
|
||||
operand = operand | (1 << reg_code(r))
|
||||
end
|
||||
else
|
||||
raise "invalid operand argument #{inspect}"
|
||||
end
|
||||
write_base = 1
|
||||
if (opcode == :push)
|
||||
pre_post_index = 1
|
||||
up_down = 0
|
||||
is_pop = 0
|
||||
else #pop
|
||||
pre_post_index = 0
|
||||
up_down = 1
|
||||
is_pop = 1
|
||||
end
|
||||
instuction_class = 0b10 # OPC_STACK
|
||||
cond = @attributes[:condition_code].is_a?(Symbol) ? COND_CODES[@attributes[:condition_code]] : @attributes[:condition_code]
|
||||
@rn = :sp # sp register
|
||||
#assemble of old
|
||||
val = operand
|
||||
val = val | (reg_code(@rn) << 16)
|
||||
val = val | (is_pop << 16+4) #20
|
||||
val = val | (write_base << 16+4+ 1)
|
||||
val = val | (@attributes[:update_status] << 16+4+ 1+1)
|
||||
val = val | (up_down << 16+4+ 1+1+1)
|
||||
val = val | (pre_post_index << 16+4+ 1+1+1+1)#24
|
||||
val = val | (instuction_class << 16+4+ 1+1+1+1 +2)
|
||||
val = val | (cond << 16+4+ 1+1+1+1 +2+2)
|
||||
io.write_uint32 val
|
||||
end
|
||||
|
||||
def is_push?
|
||||
opcode == :push
|
||||
end
|
||||
def is_pop?
|
||||
!is_push?
|
||||
end
|
||||
def uses
|
||||
is_push? ? regs : []
|
||||
end
|
||||
def assigns
|
||||
is_pop? ? regs : []
|
||||
end
|
||||
def regs
|
||||
@first
|
||||
end
|
||||
def to_s
|
||||
"#{opcode} [#{@first.join(',') }] #{super}"
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
module Arm
|
||||
class MachineCode
|
||||
|
||||
def function_call into , call
|
||||
raise "Not CallSite #{call.inspect}" unless call.is_a? Register::CallSite
|
||||
raise "Not linked #{call.inspect}" unless call.function
|
||||
into.add_code call( call.function )
|
||||
raise "No return type for #{call.function.name}" unless call.function.return_type
|
||||
call.function.return_type
|
||||
end
|
||||
|
||||
def main_start context
|
||||
entry = Register::Block.new("main_entry",nil,nil)
|
||||
entry.add_code mov( :fp , 0 )
|
||||
entry.add_code call( context.function )
|
||||
entry
|
||||
end
|
||||
def main_exit context
|
||||
exit = Register::Block.new("main_exit",nil,nil)
|
||||
syscall(exit , 1)
|
||||
exit
|
||||
end
|
||||
def function_entry block, f_name
|
||||
block.add_code push( [:lr] )
|
||||
block
|
||||
end
|
||||
def function_exit entry , f_name
|
||||
entry.add_code pop( [:pc] )
|
||||
entry
|
||||
end
|
||||
|
||||
# assumes string in standard receiver reg (r2) and moves them down for the syscall
|
||||
def write_stdout function #, string
|
||||
# TODO save and restore r0
|
||||
function.mov( :r0 , 1 ) # 1 == stdout
|
||||
function.mov( :r1 , receiver_register )
|
||||
function.mov( receiver_register , :r3 )
|
||||
syscall( function.insertion_point , 4 ) # 4 == write
|
||||
end
|
||||
|
||||
# stop, do not return
|
||||
def exit function #, string
|
||||
syscall( function.insertion_point , 1 ) # 1 == exit
|
||||
end
|
||||
|
||||
|
||||
# the number (a Register::integer) is (itself) divided by 10, ie overwritten by the result
|
||||
# and the remainder is overwritten (ie an out argument)
|
||||
# not really a function, more a macro,
|
||||
def div10 function, number , remainder
|
||||
# Note about division: devision is MUCH more expensive than one would have thought
|
||||
# And coding it is a bit of a mind leap: it's all about finding a a result that gets the
|
||||
# remainder smaller than an int. i'll post some links sometime. This is from the arm manual
|
||||
tmp = function.new_local
|
||||
function.instance_eval do
|
||||
sub( remainder , number , 10 )
|
||||
sub( number , number , number , shift_lsr: 2)
|
||||
add( number , number , number , shift_lsr: 4)
|
||||
add( number , number , number , shift_lsr: 8)
|
||||
add( number , number , number , shift_lsr: 16)
|
||||
mov( number , number , shift_lsr: 3)
|
||||
add( tmp , number , number , shift_lsl: 2)
|
||||
sub( remainder , remainder , tmp , shift_lsl: 1 , update_status: 1)
|
||||
add( number , number, 1 , condition_code: :pl )
|
||||
add( remainder , remainder , 10 , condition_code: :mi )
|
||||
end
|
||||
end
|
||||
|
||||
def syscall block , num
|
||||
# This is very arm specific, syscall number is passed in r7,
|
||||
# other arguments like a c call ie 0 and up
|
||||
sys = Register::Integer.new( Register::RegisterValue.new(SYSCALL_REG) )
|
||||
ret = Register::Integer.new( Register::RegisterValue.new(RETURN_REG) )
|
||||
block.add_code mov( sys , num )
|
||||
block.add_code swi( 0 )
|
||||
#todo should write type into r1 according to syscall
|
||||
ret
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
require 'rubygems'
|
||||
require 'bundler'
|
||||
begin
|
||||
Bundler.setup(:default, :development)
|
||||
rescue Bundler::BundlerError => e
|
||||
$stderr.puts e.message
|
||||
$stderr.puts "Run `bundle install` to install missing gems"
|
||||
exit e.status_code
|
||||
end
|
||||
|
||||
if ENV['CODECLIMATE_REPO_TOKEN']
|
||||
require "codeclimate-test-reporter"
|
||||
CodeClimate::TestReporter.start
|
||||
end
|
||||
|
||||
require "minitest/autorun"
|
||||
require "minitest/unit"
|
||||
|
||||
$LOAD_PATH.unshift(File.join(File.dirname(__FILE__), '..', 'test'))
|
||||
|
||||
require 'salama'
|
||||
|
||||
# try to test that the generation of basic instructions works
|
||||
# one instruction at a time, reverse testing from objdump --demangle -Sfghxp
|
||||
# tests are named as per assembler code, ie test_mov testing mov instruction
|
||||
|
||||
module ArmHelper
|
||||
def setup
|
||||
@machine = Arm::ArmMachine
|
||||
end
|
||||
|
||||
# code is what the generator spits out, at least one instruction worth (.first)
|
||||
# the op code is wat was witten as assembler in the first place and the binary result
|
||||
def assert_code code , op , should
|
||||
assert_equal op , code.opcode
|
||||
io = StringIO.new
|
||||
code.assemble(io)
|
||||
binary = io.string
|
||||
assert_equal should.length , binary.length , "code length wrong for #{code.inspect}"
|
||||
index = 0
|
||||
binary.each_byte do |byte |
|
||||
assert_equal should[index] , byte , "byte #{index} 0x#{should[index].to_s(16)} != 0x#{byte.to_s(16)}"
|
||||
index += 1
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
require_relative 'helper'
|
||||
|
||||
class TestAdd < MiniTest::Test
|
||||
include ArmHelper
|
||||
|
||||
def test_adc
|
||||
code = @machine.adc :r1, :r3, :r5
|
||||
assert_code code , :adc , [0x05,0x10,0xb3,0xe0] #e0 b3 10 05
|
||||
end
|
||||
def test_add
|
||||
code = @machine.add :r1 , :r1, :r3
|
||||
assert_code code , :add , [0x03,0x10,0x91,0xe0] #e0 91 10 03
|
||||
end
|
||||
def test_add_const
|
||||
code = @machine.add :r1 , :r1, 0x22
|
||||
assert_code code , :add , [0x22,0x10,0x91,0xe2] #e2 91 10 22
|
||||
end
|
||||
def test_add_const_pc
|
||||
code = @machine.add :r1 , :pc, 0x22
|
||||
assert_code code , :add , [0x22,0x10,0x9f,0xe2] #e2 9f 10 22
|
||||
end
|
||||
def test_add_const_shift
|
||||
code = @machine.add( :r1 , :r1 , 0x22 , shift_lsr: 8)
|
||||
assert_code code , :add , [0x22,0x14,0x91,0xe2] #e2 91 14 23
|
||||
end
|
||||
def test_add_lst
|
||||
code = @machine.add( :r1 , :r2 , :r3 , shift_lsr: 8)
|
||||
assert_code code , :add , [0x23,0x14,0x92,0xe0] #e0 92 14 23
|
||||
end
|
||||
def test_big_add
|
||||
code = @machine.add :r1 , :r1, 0x220
|
||||
assert_code code , :add , [0x22,0x1e,0x91,0xe2] #e2 91 1e 22
|
||||
end
|
||||
|
||||
def label pos = 0x22
|
||||
l = Register::Label.new("some" , "Label")
|
||||
l.position = pos
|
||||
l
|
||||
end
|
||||
|
||||
def pest_move_object
|
||||
code = @machine.add( :r1 , label)
|
||||
assert_code code , :add , [0x22,0x10,0x9f,0xe2] #e2 9f 10 22
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
require_relative "test_stack"
|
||||
require_relative "test_control"
|
||||
require_relative "test_logic"
|
||||
require_relative "test_add"
|
||||
require_relative "test_move"
|
||||
require_relative "test_memory"
|
||||
require_relative "test_compare"
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
require_relative 'helper'
|
||||
|
||||
class TestArmAsm < MiniTest::Test
|
||||
include ArmHelper
|
||||
|
||||
def test_cmn
|
||||
code = @machine.cmn :r1 , :r2
|
||||
assert_code code , :cmn , [0x02,0x00,0x71,0xe1] #e1 71 00 02
|
||||
end
|
||||
def test_cmp
|
||||
code = @machine.cmp :r1 , :r2
|
||||
assert_code code , :cmp , [0x02,0x00,0x51,0xe1] #e1 51 00 02
|
||||
end
|
||||
def test_teq
|
||||
code = @machine.teq :r1 , :r2
|
||||
assert_code code , :teq , [0x02,0x00,0x31,0xe1] #e1 31 00 02
|
||||
end
|
||||
def test_tst
|
||||
code = @machine.tst :r1 , :r2
|
||||
assert_code code , :tst , [0x02,0x00,0x11,0xe1] #e1 11 00 02
|
||||
end
|
||||
def test_tst2
|
||||
code = @machine.tst :r1 , :r1
|
||||
assert_code code , :tst , [0x01,0x00,0x11,0xe1] #e1 11 00 01
|
||||
end
|
||||
def test_tst3
|
||||
code = @machine.tst :r2 , :r2
|
||||
assert_code code , :tst , [0x02,0x00,0x12,0xe1] #e1 12 00 02
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
require_relative 'helper'
|
||||
|
||||
class TestControl < MiniTest::Test
|
||||
include ArmHelper
|
||||
|
||||
def test_b
|
||||
# the address is what an assembler calculates (a signed number for the amount of instructions),
|
||||
# ie the relative (to pc) address -8 (pipeline) /4 so save space
|
||||
# so the cpu adds the value*4 and starts loading that (load, decode, execute)
|
||||
code = @machine.b -4 #this jumps to the next instruction
|
||||
assert_code code , :b , [0xff,0xff,0xff,0xea] #ea ff ff fe
|
||||
end
|
||||
def test_call #see comment above. bx not implemented (as it means into thumb, and no thumb here)
|
||||
code = @machine.call -4 ,{} #this jumps to the next instruction
|
||||
assert_code code , :call, [0xff,0xff,0xff,0xeb] #ea ff ff fe
|
||||
end
|
||||
def test_swi
|
||||
code = @machine.swi 0x05
|
||||
assert_code code , :swi , [0x05,0x00,0x00,0xef]#ef 00 00 05
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
require_relative 'helper'
|
||||
|
||||
class TestLogic < MiniTest::Test
|
||||
include ArmHelper
|
||||
|
||||
def test_mul1
|
||||
code = @machine.mul( :r0 , :r1 , :r2)
|
||||
assert_code code , :mul , [0x91,0x02,0x10,0xe0] #e0 10 02 91
|
||||
end
|
||||
def test_mul2
|
||||
code = @machine.mul( :r1 , :r2 , :r3)
|
||||
assert_code code , :mul , [0x92,0x03,0x11,0xe0] #e0 11 03 92
|
||||
end
|
||||
def test_mul3
|
||||
code = @machine.mul( :r2 , :r3 , :r4)
|
||||
assert_code code , :mul , [0x93,0x04,0x12,0xe0] #e0 12 04 93
|
||||
end
|
||||
def test_and
|
||||
code = @machine.and( :r1 , :r2 , :r3)
|
||||
assert_code code , :and , [0x03,0x10,0x12,0xe0] #e0 12 10 03
|
||||
end
|
||||
def test_bic
|
||||
code = @machine.bic :r2 , :r2 , :r3
|
||||
assert_code code , :bic , [0x03,0x20,0xd2,0xe1] #e3 d2 20 44
|
||||
end
|
||||
def test_eor
|
||||
code = @machine.eor :r2 , :r2 , :r3
|
||||
assert_code code , :eor , [0x03,0x20,0x32,0xe0] #e0 32 20 03
|
||||
end
|
||||
def test_rsb
|
||||
code = @machine.rsb :r1 , :r2 , :r3
|
||||
assert_code code , :rsb , [0x03,0x10,0x72,0xe0]#e0 72 10 03
|
||||
end
|
||||
def test_rsc
|
||||
code = @machine.rsc :r2 , :r3 , :r4
|
||||
assert_code code , :rsc , [0x04,0x20,0xf3,0xe0]#e0 f3 20 04
|
||||
end
|
||||
def test_sbc
|
||||
code = @machine.sbc :r3, :r4 , :r5
|
||||
assert_code code , :sbc , [0x05,0x30,0xd4,0xe0]#e0 d4 30 05
|
||||
end
|
||||
def test_sub
|
||||
code = @machine.sub :r2, :r0, 1
|
||||
assert_code code, :sub , [0x01,0x20,0x50,0xe2] #e2 50 20 01
|
||||
end
|
||||
def test_subs
|
||||
code = @machine.sub :r2, :r2, 1 , update_status: 1
|
||||
assert_code code, :sub , [0x01,0x20,0x52,0xe2] #e2 52 20 01
|
||||
end
|
||||
def test_orr
|
||||
code = @machine.orr :r2 , :r2 , :r3
|
||||
assert_code code , :orr , [0x03,0x20,0x92,0xe1] #e1 92 20 03
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
require_relative 'helper'
|
||||
|
||||
class TestMemory < MiniTest::Test
|
||||
include ArmHelper
|
||||
|
||||
def test_ldr
|
||||
code = @machine.ldr :r0, :r0
|
||||
assert_code code, :ldr , [0x00,0x00,0x90,0xe5] #e5 90 00 00
|
||||
end
|
||||
def test_ldr_const_offset
|
||||
code = @machine.ldr :r0, :r0 , 4
|
||||
assert_code code, :ldr , [0x04,0x00,0x90,0xe5] #e5 90 00 04
|
||||
end
|
||||
def test_ldr_reg_offset
|
||||
code = @machine.ldr :r3, :r4 , :r5
|
||||
assert_code code, :ldr , [0x05,0x30,0x94,0xe7] #e7 94 30 05
|
||||
end
|
||||
def test_ldr_reg_shift2
|
||||
code = @machine.ldr :r3, :r4 , :r5 , :shift_lsl => 2
|
||||
assert_code code, :ldr , [0x05,0x31,0x94,0xe7] #e7 94 31 05
|
||||
end
|
||||
def test_ldr_reg_shift3
|
||||
code = @machine.ldr :r3, :r4 , :r5 , :shift_lsl => 3
|
||||
assert_code code, :ldr , [0x85,0x31,0x94,0xe7] #e7 94 31 85
|
||||
end
|
||||
def test_ldrb
|
||||
code = @machine.ldrb :r0, :r0
|
||||
assert_code code, :ldrb , [0x00,0x00,0xd0,0xe5] #e5 d0 00 00
|
||||
end
|
||||
def test_ldrb_const
|
||||
code = @machine.ldrb :r0, :r0 , 12
|
||||
assert_code code, :ldrb , [0x0c,0x00,0xd0,0xe5] #e5 d0 00 0c
|
||||
end
|
||||
def test_ldrb_reg_offset
|
||||
code = @machine.ldrb :r0, :r1 , :r2
|
||||
assert_code code, :ldrb , [0x02,0x00,0xd1,0xe7] #e7 d1 00 02
|
||||
end
|
||||
|
||||
def test_str
|
||||
code = @machine.str :r0, :r1
|
||||
assert_code code, :str , [0x00,0x00,0x81,0xe5] #e5 81 00 00
|
||||
end
|
||||
def test_str_const_offset
|
||||
code = @machine.str :r1, :r2 , 4
|
||||
assert_code code, :str , [0x04,0x10,0x82,0xe5] #e5 82 10 04
|
||||
end
|
||||
def test_str_reg_offset
|
||||
code = @machine.str :r3, :r4 , :r5
|
||||
assert_code code, :str , [0x05,0x30,0x84,0xe7] #e7 84 30 05
|
||||
end
|
||||
def test_str_reg_shift
|
||||
code = @machine.str :r3, :r4 , :r5 , :shift_lsl => 2
|
||||
assert_code code, :str , [0x05,0x31,0x84,0xe7] #e7 84 31 05
|
||||
end
|
||||
|
||||
def test_strb_inc #THIS IS BROKEN, but so is gnu as, as it produces same output for ! or not
|
||||
code = @machine.strb :r0, :r2 , 1 , pre_post_index: 1 # pre_post_index is autoinc (r2 here)
|
||||
assert_code code, :strb , [0x01,0x00,0xc2,0xe5] #e5 e2 00 01
|
||||
end
|
||||
|
||||
def test_strb
|
||||
code = @machine.strb :r0, :r0
|
||||
assert_code code, :strb , [0x00,0x00,0xc0,0xe5] #e5 c0 00 00
|
||||
end
|
||||
|
||||
def test_strb_const
|
||||
code = @machine.strb :r1, :r2 , 4
|
||||
assert_code code, :strb , [0x04,0x10,0xc2,0xe5] #e5 c2 10 04
|
||||
end
|
||||
def test_strb_reg_offset
|
||||
code = @machine.strb :r1, :r2 , :r3
|
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assert_code code, :strb , [0x03,0x10,0xc2,0xe7] #e7 c2 10 03
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
require_relative 'helper'
|
||||
|
||||
class TestMoves < MiniTest::Test
|
||||
include ArmHelper
|
||||
|
||||
def test_mov
|
||||
code = @machine.mov :r1, 5
|
||||
assert_code code , :mov , [0x05,0x10,0xb0,0xe3] #e3 b0 10 05
|
||||
end
|
||||
def test_mov_pc
|
||||
code = @machine.mov :pc, 5
|
||||
assert_code code , :mov , [0x05,0xf0,0xb0,0xe3] #e3 b0 f0 06
|
||||
end
|
||||
def test_mov_max_128
|
||||
code = @machine.mov :r1, 128
|
||||
assert_code code , :mov , [0x80,0x10,0xb0,0xe3] #e3 b0 10 80
|
||||
end
|
||||
def test_mov_256
|
||||
code = @machine.mov :r1, 256
|
||||
assert_code code , :mov , [0x01,0x1c,0xb0,0xe3] #e3 b0 1c 01
|
||||
end
|
||||
def test_mov_big
|
||||
code = @machine.mov :r0, 0x222 # is not 8 bit and can't be rotated by the arm system in one instruction
|
||||
code.set_position(0)
|
||||
begin # mov 512(0x200) = e3 a0 0c 02 add 34(0x22) = e2 90 00 22
|
||||
assert_code code , :mov , [ 0x02,0x0c,0xb0,0xe3 , 0x22,0x00,0x90,0xe2]
|
||||
rescue Register::LinkException
|
||||
retry
|
||||
end
|
||||
end
|
||||
def test_mvn
|
||||
code = @machine.mvn :r1, 5
|
||||
assert_code code , :mvn , [0x05,0x10,0xf0,0xe3] #e3 f0 10 05
|
||||
end
|
||||
|
||||
def test_shiftr1
|
||||
code = @machine.mov :r1, :r2 , :shift_asr => Register::RegisterValue.new(:r3 , :Integer)
|
||||
assert_code code , :mov , [0x52,0x13,0xb0,0xe1] #e1 b0 13 52
|
||||
end
|
||||
def test_shiftr2
|
||||
code = @machine.mov :r2, :r3 , :shift_asr => Register::RegisterValue.new(:r4 , :Integer)
|
||||
assert_code code , :mov , [0x53,0x24,0xb0,0xe1] #e1 b0 24 53
|
||||
end
|
||||
def test_shiftr3
|
||||
code = @machine.mov :r3, :r4 , :shift_asr => Register::RegisterValue.new(:r5 , :Integer)
|
||||
assert_code code , :mov , [0x54,0x35,0xb0,0xe1] #e1 b0 35 54
|
||||
end
|
||||
|
||||
def test_shiftl1
|
||||
code = @machine.mov :r1, :r2 , :shift_lsr => Register::RegisterValue.new(:r3 , :Integer)
|
||||
assert_code code , :mov , [0x32,0x13,0xb0,0xe1] #e1 b0 13 32
|
||||
end
|
||||
def test_shiftl2
|
||||
code = @machine.mov :r2, :r3 , :shift_lsr => Register::RegisterValue.new(:r4 , :Integer)
|
||||
assert_code code , :mov , [0x33,0x24,0xb0,0xe1] #e1 b0 24 33
|
||||
end
|
||||
def test_shiftl3
|
||||
code = @machine.mov :r3, :r4 , :shift_lsr => Register::RegisterValue.new(:r5 , :Integer)
|
||||
assert_code code , :mov , [0x34,0x35,0xb0,0xe1] #e1 b0 35 34
|
||||
end
|
||||
|
||||
end
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
require_relative 'helper'
|
||||
|
||||
class TestStack < MiniTest::Test
|
||||
include ArmHelper
|
||||
|
||||
def test_push
|
||||
code = @machine.push [:lr]
|
||||
assert_code code , :push , [0x00,0x40,0x2d,0xe9] #e9 2d 40 00
|
||||
end
|
||||
def test_push_three
|
||||
code = @machine.push [:r0,:r1,:lr]
|
||||
assert_code code , :push , [0x03,0x40,0x2d,0xe9] #e9 2d 40 03
|
||||
end
|
||||
def test_push_no_link
|
||||
code = @machine.push [:r0,:r1,:r2 ,:r3,:r4,:r5]
|
||||
assert_code code , :push , [0x3f,0x00,0x2d,0xe9] #e9 2d 00 3f
|
||||
end
|
||||
def test_pop
|
||||
code = @machine.pop [:pc]
|
||||
assert_code code , :pop , [0x00,0x80,0xbd,0xe8] #e8 bd 80 00
|
||||
end
|
||||
def test_pop_three
|
||||
code = @machine.pop [:r0,:r1,:pc]
|
||||
assert_code code , :pop , [0x03,0x80,0xbd,0xe8] #e8 bd 80 03
|
||||
end
|
||||
def test_pop_no_pc
|
||||
code = @machine.pop [:r0,:r1,:r2 ,:r3,:r4,:r5]
|
||||
assert_code code , :pop , [0x3f,0x00,0xbd,0xe8] #e8 bd 00 3f
|
||||
end
|
||||
|
||||
end
|
||||
|
|
@ -1,3 +1,5 @@
|
|||
require_relative "arm/test_all"
|
||||
|
||||
require_relative "elf/test_all"
|
||||
|
||||
require_relative "lib/test_all"
|
||||
|
|
|
|||
Loading…
Reference in New Issue