another million index fixes

This commit is contained in:
Torsten Ruger
2018-05-14 15:17:04 +03:00
parent 4a88f342d3
commit 3c00239f36
21 changed files with 72 additions and 65 deletions

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@ -21,7 +21,7 @@ module Arm
# if an instruction is passed in we get the index with index function
def arm_index( index )
index = index.index if index.is_a?(Risc::Instruction)
raise "index error 0" if index == 0
raise "index error #{index}" if index < 0
index * 4
end

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@ -92,7 +92,7 @@ module Parfait
end
def add_local( name , type )
index = has_local name
index = has_local( name )
return index if index
@frame_type = @frame_type.add_instance_variable(name,type)
end

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@ -13,7 +13,7 @@ module Risc
# Go through and assemble all instructions.
def assemble( instruction )
@index = 1
@index = 0
while(instruction)
instruction.assemble(self)
instruction = instruction.next

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@ -59,8 +59,8 @@ module Risc
space = Parfait::Space.new( classes )
Parfait.set_object_space( space )
#puts Sof.write(space)
#boot_functions( space )
#puts Rfx.write(space)
boot_functions( space )
end
# types is where the snake bites its tail. Every chain ends at a type and then it

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@ -103,7 +103,7 @@ module Risc
# return both registers
def self_and_int_arg( source )
me = add_known( :receiver )
int_arg = load_int_arg_at(source , 1 )
int_arg = load_int_arg_at(source , 0 )
return me , int_arg
end
@ -114,7 +114,7 @@ module Risc
add_slot_to_reg(source , int_arg , at + 1, int_arg ) #1 for type
return int_arg
end
# assumed Integer in given register is replaced by the fixnum that it is holding
def reduce_int( source , register )
add_slot_to_reg( source + "int -> fix" , register , Parfait::Integer.integer_index , register)

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@ -27,8 +27,7 @@ module Risc
source = "set_internal_word"
builder = compiler.builder(true, compiler.method)
me , index = builder.self_and_int_arg(source)
value = builder.load_int_arg_at(source , 2)
value = builder.load_int_arg_at(source , 1)
# do the set
builder.add_reg_to_slot( source , value , me , index)
compiler.add_mom( Mom::ReturnSequence.new)

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@ -41,7 +41,7 @@ module Risc
source = "set_internal_byte"
builder = compiler.builder(true, compiler.method)
me , index = builder.self_and_int_arg(source)
value = builder.load_int_arg_at(source , 2 )
value = builder.load_int_arg_at(source , 1 )
builder.reduce_int( source + " fix me", value )
builder.reduce_int( source + " fix arg", index )
builder.add_reg_to_byte( source , value , me , index)

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@ -18,9 +18,14 @@ module Risc
# (which are precisely the symbols :message or :new_message. or a register)
# index resolves with resolve_to_index.
def self.reg_to_slot( source , from_reg , to , index )
no_rec = index != :receiver
puts "FROM #{from_reg}"
puts "TO #{to}"
puts "IN #{index}"
from = resolve_to_register from_reg
index = resolve_to_index( to , index)
to = resolve_to_register to
# raise "HALLO " if index == 2 and no_rec
RegToSlot.new( source, from , to , index)
end

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@ -21,7 +21,7 @@ module Risc
@register = register
@array = array
@index = index
raise "index 0 " if index < 0
# raise "index 0 " if index < 0
raise "Not integer or reg #{index}" unless index.is_a?(Numeric) or RiscValue.look_like_reg(index)
raise "Not register #{register}" unless RiscValue.look_like_reg(register)
raise "Not register #{array}" unless RiscValue.look_like_reg(array)

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@ -153,6 +153,7 @@ module Risc
else
index = get_register(@instruction.index)
end
puts "INDEX #{index} #{value}"
object.set_internal_word( index , value )
trigger(:object_changed, @instruction.array , index)
true

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@ -144,6 +144,7 @@ module Risc
end
def write_data4( code )
write_ref_for( code.get_type )
write_ref_for( code.get_type )
log.debug "Data4 witten stream 0x#{@stream.length.to_s(16)}"
end
@ -161,6 +162,7 @@ module Risc
code.each_word do |word|
@stream.write_unsigned_int_32( word || 0 )
end
write_ref_for( code.get_type )
log.debug "Code16 witten stream 0x#{@stream.length.to_s(16)}"
end