2017-01-19 08:02:29 +01:00
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module Risc
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2014-10-04 11:51:08 +02:00
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2018-03-21 11:18:04 +01:00
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# Transfer the constents of one register to another.
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2015-06-21 20:00:16 +02:00
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# possibly called move in some cpus
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2014-10-04 11:51:08 +02:00
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2016-12-25 17:05:39 +01:00
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# There are other instructions to move data from / to memory, namely SlotToReg and RegToSlot
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2015-06-21 20:00:16 +02:00
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# Get/Set Slot move data around in vm objects, but transfer moves the objects (in the machine)
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#
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# Also it is used for moving temorary data
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2015-06-27 19:09:21 +02:00
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#
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2018-03-21 11:18:04 +01:00
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class Transfer < Instruction
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2015-06-27 19:09:21 +02:00
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# initialize with from and to registers.
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# First argument from
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2015-10-14 12:48:42 +02:00
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# second argument to
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2015-06-27 19:09:21 +02:00
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#
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2015-07-24 12:23:56 +02:00
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# Note: this may be reversed from some assembler notations (also arm)
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2018-03-21 11:18:04 +01:00
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def initialize( source , from , to )
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2015-07-27 11:13:39 +02:00
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super(source)
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2015-10-15 08:32:47 +02:00
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@from = from
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@to = to
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2018-06-29 10:39:07 +02:00
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raise "Fix me #{from}" unless from.is_a? RegisterValue
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raise "Fix me #{to}" unless to.is_a? RegisterValue
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2014-10-04 11:51:08 +02:00
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end
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attr_reader :from, :to
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2015-07-24 12:23:56 +02:00
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2020-03-18 16:49:23 +01:00
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# return an array of names of registers that is used by the instruction
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2020-03-20 12:58:40 +01:00
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def register_attributes
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[:from , :to]
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2020-03-18 16:49:23 +01:00
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end
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2015-07-24 12:23:56 +02:00
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def to_s
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2018-03-22 17:38:19 +01:00
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class_source "#{from} -> #{to}"
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2015-07-24 12:23:56 +02:00
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end
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2015-11-21 13:17:54 +01:00
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end
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2016-12-28 17:37:15 +01:00
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def self.transfer( source , from , to)
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2018-03-21 11:18:04 +01:00
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Transfer.new( source , from , to)
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2014-10-04 11:51:08 +02:00
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end
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2015-06-21 20:00:16 +02:00
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end
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