2014-08-30 18:40:37 +02:00
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module Arm
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class MoveInstruction < Register::MoveInstruction
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include Arm::Constants
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def initialize(to , from , attributes)
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super(to , from , attributes)
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@attributes[:update_status] = 0 if @attributes[:update_status] == nil
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@attributes[:condition_code] = :al if @attributes[:condition_code] == nil
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@attributes[:opcode] = attributes[:opcode]
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@operand = 0
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@immediate = 0
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@rn = :r0 # register zero = zero bit pattern
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2014-09-16 10:39:08 +02:00
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@from = Virtual::IntegerConstant.new( @from ) if( @from.is_a? Fixnum )
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2014-08-30 18:40:37 +02:00
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end
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# arm intrucions are pretty sensible, and always 4 bytes (thumb not supported)
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2014-09-16 10:39:08 +02:00
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# but not all constants fit into the part of the instruction that is left after the instruction code,
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# so large moves have to be split into two instrucitons. we handle this here, just this instruciton looks
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# longer
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2014-09-16 16:16:13 +02:00
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def mem_length
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return 4
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2014-09-16 10:39:08 +02:00
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is_simple ? 4 : 8
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end
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# a constant (the one we want to move) can either be < 256 or be rotated in a funny arm way
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# if neither works (not simple !) we need two instructions to make the move
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def is_simple
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right = @from
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if right.is_a?(Virtual::ObjectConstant)
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2014-09-16 16:16:13 +02:00
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r_pos = right.position
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2014-09-16 10:39:08 +02:00
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# do pc relative addressing with the difference to the instuction
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# 8 is for the funny pipeline adjustment (ie pc pointing to fetch and not execute)
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right = Virtual::IntegerConstant.new( r_pos - self.position - 8 )
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end
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if (right.is_a?(Virtual::IntegerConstant))
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if (right.integer.fits_u8?)
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return true
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elsif (calculate_u8_with_rr(right))
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return true
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else
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return false
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end
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end
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return true
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2014-08-30 18:40:37 +02:00
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end
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2014-09-16 16:16:13 +02:00
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def assemble(io)
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2014-08-30 18:40:37 +02:00
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# don't overwrite instance variables, to make assembly repeatable
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rn = @rn
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operand = @operand
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immediate = @immediate
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2014-09-16 10:39:08 +02:00
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complex = false
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2014-08-30 18:40:37 +02:00
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right = @from
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if right.is_a?(Virtual::ObjectConstant)
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2014-09-16 16:16:13 +02:00
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r_pos = right.position
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2014-08-30 18:40:37 +02:00
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# do pc relative addressing with the difference to the instuction
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2014-09-16 10:39:08 +02:00
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# 8 is for the funny pipeline adjustment (ie pc pointing to fetch and not execute)
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right = Virtual::IntegerConstant.new( r_pos - self.position - 8 )
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puts "Position #{r_pos} from #{self.position} = #{right}"
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right = Virtual::IntegerConstant.new(r_pos) if right.integer > 255
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2014-08-30 18:40:37 +02:00
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rn = :pc
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end
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if (right.is_a?(Virtual::IntegerConstant))
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if (right.integer.fits_u8?)
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# no shifting needed
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operand = right.integer
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immediate = 1
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elsif (op_with_rot = calculate_u8_with_rr(right))
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operand = op_with_rot
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immediate = 1
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raise "hmm"
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else
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2014-09-17 11:04:54 +02:00
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operand = right.integer / 256
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immediate = 1
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# raise "cannot fit numeric literal argument in operand #{right.inspect}"
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2014-08-30 18:40:37 +02:00
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end
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elsif (right.is_a?(Symbol) or right.is_a?(Virtual::Integer))
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operand = reg_code(right) #integer means the register the integer is in (otherwise constant)
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immediate = 0 # ie not immediate is register
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else
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raise "invalid operand argument #{right.inspect} , #{inspect}"
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end
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op = shift_handling
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instuction_class = 0b00 # OPC_DATA_PROCESSING
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val = shift(operand , 0)
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2014-09-16 10:39:08 +02:00
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val |= shift(op , 0) # any barrel action, is already shifted
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2014-08-30 18:40:37 +02:00
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val |= shift(reg_code(@to) , 12)
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val |= shift(reg_code(rn) , 12+4)
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val |= shift(@attributes[:update_status] , 12+4+4)#20
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val |= shift(op_bit_code , 12+4+4 +1)
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val |= shift(immediate , 12+4+4 +1+4)
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val |= shift(instuction_class , 12+4+4 +1+4+1)
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val |= shift(cond_bit_code , 12+4+4 +1+4+1+2)
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io.write_uint32 val
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end
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def shift val , by
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raise "Not integer #{val}:#{val.class} in #{inspect}" unless val.is_a? Fixnum
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val << by
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end
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end
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end
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