2015-10-24 10:42:36 +02:00
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module Arm
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2018-03-26 18:42:15 +02:00
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# A translator is cpu specific and translates from risc instructions to a given
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2018-03-28 11:50:07 +02:00
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# cpu. This one transltes to Arm Instructions.
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2015-10-24 10:42:36 +02:00
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class Translator
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2015-10-24 16:11:18 +02:00
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# translator should translate from register instructio set to it's own (arm eg)
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# for each instruction we call the translator with translate_XXX
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# with XXX being the class name.
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# the result is replaced in the stream
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2018-03-11 11:41:15 +01:00
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def translate( instruction )
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2015-10-24 16:11:18 +02:00
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class_name = instruction.class.name.split("::").last
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self.send( "translate_#{class_name}".to_sym , instruction)
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end
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2018-03-11 11:41:15 +01:00
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def translate_Label( code )
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2018-05-30 23:07:58 +02:00
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Risc.label( code.source , code.name , code.address)
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2015-10-24 10:42:36 +02:00
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end
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2015-11-14 23:35:12 +01:00
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# arm indexes are
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# in bytes, so *4
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2015-11-15 19:42:07 +01:00
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# if an instruction is passed in we get the index with index function
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2018-03-11 11:41:15 +01:00
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def arm_index( index )
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2017-01-19 08:02:29 +01:00
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index = index.index if index.is_a?(Risc::Instruction)
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2018-05-14 14:17:04 +02:00
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raise "index error #{index}" if index < 0
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2015-11-15 19:42:07 +01:00
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index * 4
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2015-11-14 23:35:12 +01:00
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end
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2015-10-24 10:42:36 +02:00
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2018-03-21 11:18:04 +01:00
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def translate_Transfer( code )
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2017-01-19 08:02:29 +01:00
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# Risc machine convention is from => to
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2015-11-19 09:09:55 +01:00
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# But arm has the receiver/result as the first
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ArmMachine.mov( code.to , code.from)
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end
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2016-12-25 17:05:39 +01:00
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def translate_SlotToReg( code )
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2016-12-15 17:21:08 +01:00
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ArmMachine.ldr( *slot_args_for(code) )
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2015-10-24 10:42:36 +02:00
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end
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2016-12-25 17:02:39 +01:00
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def translate_RegToSlot( code )
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2016-12-15 17:21:08 +01:00
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ArmMachine.str( *slot_args_for(code) )
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end
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def slot_args_for( code )
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2015-11-08 16:10:36 +01:00
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if(code.index.is_a? Numeric)
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2016-12-15 17:21:08 +01:00
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[ code.register , code.array , arm_index(code) ]
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2015-11-08 16:10:36 +01:00
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else
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2016-12-15 17:21:08 +01:00
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[ code.register , code.array , code.index , :shift_lsl => 2]
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2015-11-08 16:10:36 +01:00
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end
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2015-10-24 10:42:36 +02:00
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end
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2016-12-15 17:21:08 +01:00
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def byte_args_for( code )
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args = slot_args_for( code )
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args.pop if(code.index.is_a? Numeric)
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args
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end
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2018-03-28 11:50:07 +02:00
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def translate_ByteToReg( code )
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2016-12-15 17:21:08 +01:00
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ArmMachine.ldrb( *byte_args_for(code) )
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2015-11-19 09:09:55 +01:00
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end
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2018-03-28 11:50:07 +02:00
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def translate_RegToByte( code )
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2016-12-15 17:21:08 +01:00
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ArmMachine.strb( *byte_args_for(code) )
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2015-11-19 09:09:55 +01:00
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end
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2018-03-28 11:50:07 +02:00
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def translate_FunctionCall( code )
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ArmMachine.b( code.method.binary )
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2015-10-24 10:42:36 +02:00
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end
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2018-06-24 18:13:55 +02:00
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def translate_FunctionReturn( code )
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2020-03-13 15:25:35 +01:00
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# FIXME reduce the int first, register contains a ReturnAddress
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2018-03-28 11:50:07 +02:00
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ArmMachine.mov( :pc , code.register)
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2015-10-24 10:42:36 +02:00
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end
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2018-06-24 23:19:43 +02:00
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def translate_DynamicJump(code)
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2018-07-13 20:50:40 +02:00
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index = Parfait.object_space.get_type_by_class_name(:CallableMethod).variable_index(:binary)
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2018-06-24 23:19:43 +02:00
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codes = ArmMachine.ldr( code.register , code.register , arm_index(index) )
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codes << ArmMachine.mov( :pc , code.register)
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codes
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end
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2015-10-24 10:42:36 +02:00
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2018-03-28 11:50:07 +02:00
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def translate_LoadConstant( code )
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2015-10-24 10:42:36 +02:00
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constant = code.constant
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2018-03-28 11:50:07 +02:00
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constant = constant.to_cpu(self) if constant.is_a?(Risc::Label)
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2018-03-31 11:38:30 +02:00
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return ArmMachine.add( code.register , constant )
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end
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def translate_LoadData( code )
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return ArmMachine.mov( code.register , code.constant )
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2015-10-24 10:42:36 +02:00
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end
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2018-03-30 16:09:02 +02:00
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def translate_OperatorInstruction( code )
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2015-11-12 19:02:14 +01:00
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left = code.left
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right = code.right
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case code.operator.to_s
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when "+"
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c = ArmMachine.add(left , left , right)
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when "-"
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c = ArmMachine.sub(left , left , right)
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when "&"
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c = ArmMachine.and(left , left , right)
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when "|"
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c = ArmMachine.orr(left , left , right)
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when "*"
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c = ArmMachine.mul(left , right , left) #arm rule about left not being result, lukily commutative
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2015-11-13 23:20:03 +01:00
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when ">>"
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c = ArmMachine.mov(left , left , :shift_asr => right) #arm rule about left not being result, lukily commutative
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when "<<"
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c = ArmMachine.mov(left , left , :shift_lsl => right) #arm rule about left not being result, lukily commutative
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2015-11-12 19:02:14 +01:00
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else
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raise "unimplemented '#{code.operator}' #{code}"
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end
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c
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end
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2015-10-24 10:42:36 +02:00
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# This implements branch logic, which is simply assembler branch
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#
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# The only target for a call is a Block, so we just need to get the address for the code
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# and branch to it.
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2018-03-28 11:50:07 +02:00
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def translate_Branch( code )
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2018-05-25 18:04:48 +02:00
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target = code.label.is_a?(Risc::Label) ? code.label.to_cpu(self) : code.label
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ArmMachine.b( target )
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2015-10-24 10:42:36 +02:00
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end
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2015-10-24 16:11:18 +02:00
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2018-03-28 11:50:07 +02:00
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def translate_IsPlus( code )
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ArmMachine.bpl( code.label.to_cpu(self) )
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2015-11-13 23:20:03 +01:00
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end
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2018-03-28 11:50:07 +02:00
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def translate_IsMinus( code )
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ArmMachine.bmi( code.label.to_cpu(self) )
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2015-11-13 23:20:03 +01:00
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end
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2018-03-28 11:50:07 +02:00
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def translate_IsZero( code )
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ArmMachine.beq( code.label.to_cpu(self) )
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2018-04-02 18:31:08 +02:00
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end
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def translate_IsNotZero( code )
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ArmMachine.bne( code.label.to_cpu(self) )
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2015-11-13 23:20:03 +01:00
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end
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2018-03-28 11:50:07 +02:00
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def translate_IsOverflow( code )
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ArmMachine.bvs( code.label.to_cpu(self))
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2015-11-13 23:20:03 +01:00
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end
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2018-03-28 11:50:07 +02:00
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def translate_Syscall( code )
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2019-09-09 10:47:37 +02:00
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call_codes = { putstring: 4 , exit: 1 }
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name = code.name
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name = :exit if name == :died
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int_code = call_codes[name]
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raise "Not implemented syscall, #{name}" unless int_code
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send( name , int_code )
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2015-10-24 10:42:36 +02:00
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end
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2019-09-24 11:58:31 +02:00
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def putstring( int_code ) # adjust for object header (0 based, hence -1)
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codes = ArmMachine.add( :r1 , :r1 , (Parfait::Word.type_length - 1)*4 )
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2015-11-15 10:28:16 +01:00
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codes.append ArmMachine.mov( :r0 , 1 ) # write to stdout == 1
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2015-10-24 10:42:36 +02:00
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syscall(int_code , codes )
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end
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2018-03-28 11:50:07 +02:00
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def exit( int_code )
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2018-06-19 18:52:06 +02:00
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codes = ArmMachine.mov( :r7 , int_code )
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codes.append ArmMachine.swi( 0 )
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codes
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2015-10-24 10:42:36 +02:00
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end
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private
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# syscall is always triggered by swi(0)
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# The actual code (ie the index of the kernel function) is in r7
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2018-06-19 18:52:06 +02:00
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def syscall( int_code , codes)
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2015-10-24 10:42:36 +02:00
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codes.append ArmMachine.mov( :r7 , int_code )
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codes.append ArmMachine.swi( 0 )
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codes
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end
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end
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end
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