2018-03-26 18:46:38 +02:00
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require "util/list"
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2014-05-03 14:13:44 +02:00
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2018-03-18 06:06:01 +01:00
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module Risc
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2015-10-23 20:27:36 +02:00
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2018-03-18 06:06:01 +01:00
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# the register machine has at least 8 registers, named r0-r5 , :lr and :pc
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# (for historical reasons , r for register, pc for ProgramCounter ie next instruction address
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# and lr means LinkRegister, ie the location where to return to when in a function)
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#
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# We can load and store their contents, move data between them and
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# access (get/set) memory at a constant offset from a register
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2019-10-03 19:55:41 +02:00
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# While SlotMachine works with objects, the register machine has registers,
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2018-03-18 06:06:01 +01:00
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# but we keep the names for better understanding, r2-5 are temporary/scratch
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# There is no direct memory access, only through registers
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# Constants can/must be loaded into registers before use
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# At compile time, Instructions form a linked list (:next attribute is the link)
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# At run time Instructions are traversesed as a graph
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#
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2015-10-23 20:27:36 +02:00
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# Branches fan out, Labels collect
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# Labels are the only valid branch targets
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2018-03-18 06:06:01 +01:00
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#
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2014-10-03 09:25:10 +02:00
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class Instruction
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2018-03-26 19:05:30 +02:00
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include Util::List
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2014-10-03 09:25:10 +02:00
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2018-03-26 19:05:30 +02:00
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def initialize( source , nekst = nil )
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2015-10-28 20:38:23 +01:00
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@source = source
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@next = nekst
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return unless source
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2018-04-18 18:27:46 +02:00
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raise "Source must be string or Instruction, not #{source.class}" unless source.is_a?(String) or
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2019-10-03 19:55:41 +02:00
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source.is_a?(SlotMachine::Instruction) or source.is_a?(Parfait::Callable)
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2015-07-18 10:21:49 +02:00
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end
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2015-07-27 11:13:39 +02:00
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attr_reader :source
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2015-07-18 10:21:49 +02:00
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2018-03-26 13:54:41 +02:00
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def to_arr
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ret = []
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self.each {|ins| ret << ins}
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2015-10-23 20:27:36 +02:00
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ret
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2014-06-08 00:41:56 +02:00
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end
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2015-10-23 20:27:36 +02:00
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2018-06-17 12:53:17 +02:00
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# just part of the protocol, noop in this case
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def precheck
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end
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2020-03-18 16:49:23 +01:00
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# return an array of names of registers that is used by the instruction
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def register_names
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raise "Not implemented in #{self.class}"
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end
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2018-03-25 18:38:59 +02:00
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def to_cpu( translator )
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translator.translate( self )
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end
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2018-03-22 17:38:19 +01:00
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def class_source( derived)
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"#{self.class.name.split("::").last}: #{derived} #{source_mini}"
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end
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def source_mini
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return "(no source)" unless source
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2018-05-23 17:05:22 +02:00
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return "(from: #{source[0..50]})" if source.is_a?(String)
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2018-03-22 17:38:19 +01:00
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"(from: #{source.class.name.split("::").last})"
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end
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2014-05-02 07:02:25 +02:00
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end
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2015-05-24 19:00:11 +02:00
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2014-05-02 07:02:25 +02:00
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end
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2014-10-03 10:05:17 +02:00
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2020-03-02 16:58:13 +01:00
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require_relative "setter"
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require_relative "getter"
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require_relative "reg_to_slot"
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require_relative "slot_to_reg"
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require_relative "reg_to_byte"
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require_relative "byte_to_reg"
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require_relative "load_constant"
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require_relative "load_data"
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require_relative "syscall"
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require_relative "function_call"
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require_relative "function_return"
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require_relative "transfer"
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require_relative "label"
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require_relative "branch"
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require_relative "dynamic_jump"
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require_relative "operator_instruction"
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