2017-01-19 09:02:29 +02:00
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module Risc
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2015-06-21 21:00:16 +03:00
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2016-12-25 18:05:39 +02:00
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# SlotToReg moves data into a register from memory.
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2016-12-25 18:02:39 +02:00
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# RegToSlot moves data into memory from a register.
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2015-06-21 21:00:16 +03:00
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# Both use a base memory (a register)
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# This is because that is what cpu's can do. In programming terms this would be accessing
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2016-12-25 18:05:39 +02:00
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# an element in an array, in the case of SlotToReg setting the value in the array.
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2015-06-21 21:00:16 +03:00
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2018-03-21 15:48:04 +05:30
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# btw: to move data between registers, use Transfer
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2015-06-21 21:00:16 +03:00
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2016-12-25 18:05:39 +02:00
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class SlotToReg < Getter
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2015-06-21 21:00:16 +03:00
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2014-10-03 11:07:18 +03:00
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end
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2015-06-30 09:43:50 +03:00
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2016-12-25 18:05:39 +02:00
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# Produce a SlotToReg instruction.
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2020-03-01 12:42:28 +02:00
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# Array is a register
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2018-07-15 16:30:50 +03:00
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# index may be a Symbol in which case is resolves with resolve_index.
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2020-03-01 12:42:28 +02:00
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# a new regsister will be created as the result, ie the reg part for slot_to_reg
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2020-02-29 17:18:27 +02:00
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def self.slot_to_reg( source , array , index )
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raise "Register #{array}" if RegisterValue.look_like_reg(array.symbol)
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2020-03-01 16:41:58 +02:00
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new_name = "#{array.symbol}.#{index.to_s.downcase}".to_sym
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2018-07-15 16:30:50 +03:00
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index = array.resolve_index(index) if index.is_a?(Symbol)
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2020-02-29 17:18:27 +02:00
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type = array.type_at(index)
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#puts "Slot for #{array.symbol}@ index #{index} is #{type}"
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2020-03-01 16:41:58 +02:00
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to = RegisterValue.new( new_name , type )
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2016-12-25 18:05:39 +02:00
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SlotToReg.new( source , array , index , to)
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2015-06-30 09:43:50 +03:00
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end
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2014-10-03 11:07:18 +03:00
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end
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