2017-01-19 08:02:29 +01:00
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module Risc
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2015-06-21 20:00:16 +02:00
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2016-12-25 17:02:39 +01:00
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# RegToSlot moves data into memory from a register.
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2016-12-25 17:05:39 +01:00
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# SlotToReg moves data into a register from memory.
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2015-06-21 20:00:16 +02:00
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# Both use a base memory (a register)
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# This is because that is what cpu's can do. In programming terms this would be accessing
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2020-03-01 11:42:28 +01:00
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# an element in an array, in the case of RegToSlot setting the register in the array.
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2015-06-21 20:00:16 +02:00
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2018-03-21 11:18:04 +01:00
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# btw: to move data between registers, use Transfer
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2015-06-21 20:00:16 +02:00
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2016-12-25 17:02:39 +01:00
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class RegToSlot < Setter
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2015-06-21 20:00:16 +02:00
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2014-10-03 10:07:18 +02:00
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end
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2015-06-30 08:43:50 +02:00
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2016-12-25 17:02:39 +01:00
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# Produce a RegToSlot instruction.
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2018-07-15 15:30:50 +02:00
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# From and to are registers
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# index may be a Symbol in which case is resolves with resolve_index.
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2020-03-01 11:42:28 +01:00
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#
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# The slot is ultimately a memory location, so no new register is created
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2018-07-15 15:30:50 +02:00
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def self.reg_to_slot( source , from , to , index )
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raise "Not register #{to}" unless RegisterValue.look_like_reg(to)
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index = to.resolve_index(index) if index.is_a?(Symbol)
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2016-12-25 17:02:39 +01:00
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RegToSlot.new( source, from , to , index)
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2015-06-30 08:43:50 +02:00
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end
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2014-10-03 10:07:18 +02:00
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end
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