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♻️ Amend of previous commit

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François Autin 2023-03-27 15:01:34 +02:00
parent 288703321e
commit ff93fab832
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GPG Key ID: 343F5D382E1DD77C
1 changed files with 1 additions and 3 deletions
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4
src/simulator/machine.rs
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@ -353,7 +353,6 @@ impl Machine {
self.int_reg.set_reg(rd, val);
Ok(())
};
match inst.funct3 {
RISCV_LD_LB | RISCV_LD_LBU => set_reg(inst.rd, 1),
RISCV_LD_LH | RISCV_LD_LHU => set_reg(inst.rd, 2),
@ -373,7 +372,6 @@ impl Machine {
);
Ok(())
};
match inst.funct3 {
RISCV_ST_STB => store(1),
RISCV_ST_STH => store(2),
@ -402,7 +400,7 @@ impl Machine {
RISCV_OPI_SRI => if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
compute(&|a, b| { (a >> b) & self.shiftmask[inst.shamt as usize] as i64 }, rs1, shamt)
} else {
compute(&|a, b| { a >> b }, rs1, shamt)
compute(&core::ops::Shr::shr, rs1, shamt)
}
_ => Err(MachineError::new(format!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value).as_str()))
}