Rativel/BurritOS
1
1
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'decode_print' of gitlab.istic.univ-rennes1.fr:simpleos/burritos into decode_print

Browse Source
This commit is contained in:
Baptiste 2023-02-01 17:14:05 +01:00
commit d04072c89a
2 changed files with 80 additions and 88 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

166
src/simulator/machine.rs
View File

@ -5,13 +5,13 @@ use super::global::*;
/// doit disparaitre /// doit disparaitre
const MEM_SIZE : usize = 4096; const MEM_SIZE : usize = 4096;
trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {} pub trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {}
impl RegisterNum for i64 {} impl RegisterNum for i64 {}
impl RegisterNum for f32 {} impl RegisterNum for f32 {}
struct Register<U: RegisterNum> { pub struct Register<U: RegisterNum> {
register: [U; 32] register: [U; 32]
} }
@ -58,7 +58,7 @@ impl Register<f32> {
pub struct Machine { pub struct Machine {
pub pc : u64, pub pc : u64,
pub int_reg : [i64 ; 32], pub int_reg : Register<i64>,
pub instructions : [u64 ; 100], pub instructions : [u64 ; 100],
pub main_memory : [u8 ; MEM_SIZE], pub main_memory : [u8 ; MEM_SIZE],
pub shiftmask : [u64 ; 64] pub shiftmask : [u64 ; 64]
@ -85,7 +85,7 @@ impl Machine {
Machine { Machine {
pc : 0, pc : 0,
instructions : [0 ; 100], instructions : [0 ; 100],
int_reg : [0 ; 32], int_reg : Register::<i64>::init(),
main_memory : [0 ; MEM_SIZE], main_memory : [0 ; MEM_SIZE],
shiftmask shiftmask
} }
@ -175,19 +175,19 @@ impl Machine {
match inst.opcode { match inst.opcode {
RISCV_LUI => { RISCV_LUI => {
machine.int_reg[inst.rd as usize] = inst.imm31_12 as i64; machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64);
}, },
RISCV_AUIPC => { RISCV_AUIPC => {
machine.int_reg[inst.rd as usize] = machine.pc as i64 - 4 + inst.imm31_12 as i64; machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64);
}, },
RISCV_JAL => { RISCV_JAL => {
machine.int_reg[inst.rd as usize] = machine.pc as i64; machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64);
machine.pc += inst.imm21_1_signed as u64 - 4; machine.pc += inst.imm21_1_signed as u64 - 4;
}, },
RISCV_JALR => { RISCV_JALR => {
let tmp = machine.pc; let tmp = machine.pc;
machine.pc = (machine.int_reg[inst.rs1 as usize] as u64 + inst.imm12_I_signed as u64) & 0xfffffffe; machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 + inst.imm12_I_signed as u64) & 0xfffffffe;
machine.int_reg[inst.rd as usize] = tmp as i64; machine.int_reg.set_reg(inst.rd as usize, tmp as i64);
}, },
//****************************************************************************************** //******************************************************************************************
@ -195,32 +195,32 @@ impl Machine {
RISCV_BR => { RISCV_BR => {
match inst.funct3 { match inst.funct3 {
RISCV_BR_BEQ => { RISCV_BR_BEQ => {
if machine.int_reg[inst.rs1 as usize] == machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RISCV_BR_BNE => { RISCV_BR_BNE => {
if machine.int_reg[inst.rs1 as usize] != machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RISCV_BR_BLT => { RISCV_BR_BLT => {
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RISCV_BR_BGE => { RISCV_BR_BGE => {
if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RISCV_BR_BLTU => { RISCV_BR_BLTU => {
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RISCV_BR_BGEU => { RISCV_BR_BGEU => {
if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
@ -234,49 +234,41 @@ impl Machine {
// Treatment for: LOAD INSTRUCTIONS // Treatment for: LOAD INSTRUCTIONS
RISCV_LD => { RISCV_LD => {
match inst.funct3 { match inst.funct3 {
RISCV_LD_LB => { RISCV_LD_LB | RISCV_LD_LBU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
machine.int_reg.set_reg(inst.rd as usize, tmp);
}, },
RISCV_LD_LH => { RISCV_LD_LH | RISCV_LD_LHU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; let tmp = Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
machine.int_reg.set_reg(inst.rd as usize, tmp);
}, },
RISCV_LD_LW => { RISCV_LD_LW | RISCV_LD_LWU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; let tmp = Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
machine.int_reg.set_reg(inst.rd as usize, tmp);
}, },
RISCV_LD_LD => { RISCV_LD_LD => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
}, machine.int_reg.set_reg(inst.rd as usize, tmp);
// same thing three opration ?
RISCV_LD_LBU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
},
RISCV_LD_LHU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
},
RISCV_LD_LWU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
}, },
_ => { _ => {
panic!("In LD switch case, this should never happen... Instr was {}", inst.value); panic!("In LD switch case, this should never happen... Instr was {}", inst.value);
} }
} }
}, },
// store instructions // store instructions
RISCV_ST => { RISCV_ST => {
match inst.funct3 { match inst.funct3 {
RISCV_ST_STB => { RISCV_ST_STB => {
Self::write_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); // Possible bugs à cause du cast ici Self::write_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
}, },
RISCV_ST_STH => { RISCV_ST_STH => {
Self::write_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); Self::write_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
}, },
RISCV_ST_STW => { RISCV_ST_STW => {
Self::write_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); Self::write_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
}, },
RISCV_ST_STD => { RISCV_ST_STD => {
Self::write_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); Self::write_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
}, },
_ => { _ => {
panic!("In ST switch case, this should never happen... Instr was {}", inst.value); panic!("In ST switch case, this should never happen... Instr was {}", inst.value);
@ -288,28 +280,28 @@ impl Machine {
RISCV_OPI => { RISCV_OPI => {
match inst.funct3 { match inst.funct3 {
RISCV_OPI_ADDI => { RISCV_OPI_ADDI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64);
}, },
RISCV_OPI_SLTI => { RISCV_OPI_SLTI => {
machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64) as i64; machine.int_reg.set_reg(inst.rd as usize, if machine.int_reg.get_reg(inst.rs1 as usize) < inst.imm12_I_signed as i64 { 1 } else { 0 } );
}, },
RISCV_OPI_XORI => { RISCV_OPI_XORI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ inst.imm12_I_signed as i64);
}, },
RISCV_OPI_ORI => { RISCV_OPI_ORI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as i64; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | inst.imm12_I_signed as i64);
}, },
RISCV_OPI_ANDI => { RISCV_OPI_ANDI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as i64; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & inst.imm12_I_signed as i64);
}, },
RISCV_OPI_SLLI => { RISCV_OPI_SLLI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << inst.shamt);
}, },
RISCV_OPI_SRI => { RISCV_OPI_SRI => {
if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {
machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64; machine.int_reg.set_reg(inst.rd as usize, (machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt) & machine.shiftmask[inst.shamt as usize] as i64);
} else { // SRAI } else { // SRAI
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> inst.shamt);
} }
} }
_ => { panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value); } _ => { panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value); }
@ -320,17 +312,17 @@ impl Machine {
if inst.funct7 == 1 { if inst.funct7 == 1 {
match inst.funct3 { match inst.funct3 {
RISCV_OP_M_MUL => { RISCV_OP_M_MUL => {
long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128;
machine.int_reg[inst.rd as usize] = (long_result & 0xffffffffffffffff) as i64; machine.int_reg.set_reg(inst.rd as usize, (long_result & 0xffffffffffffffff) as i64);
}, },
RISCV_OP_M_MULH => { RISCV_OP_M_MULH => {
long_result = (machine.int_reg[inst.rs1 as usize] * machine.int_reg[inst.rs2 as usize]) as i128; long_result = (machine.int_reg.get_reg(inst.rs1 as usize) * machine.int_reg.get_reg(inst.rs2 as usize)) as i128;
machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64);
}, },
RISCV_OP_M_MULHSU => { RISCV_OP_M_MULHSU => {
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64;
long_result = (machine.int_reg[inst.rs1 as usize] as u64 * unsigned_reg2) as i128; long_result = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 * unsigned_reg2) as i128;
machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64);
}, },
// VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve // VOIR CE QUE FAIT EXACTEMENT CE TRUC , PK on converve
/* /*
@ -338,13 +330,13 @@ impl Machine {
* WHAT DA HECK * WHAT DA HECK
*/ */
RISCV_OP_M_MULHU => { RISCV_OP_M_MULHU => {
unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64;
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64;
long_result = (unsigned_reg1 * unsigned_reg2) as i128; long_result = (unsigned_reg1 * unsigned_reg2) as i128;
machine.int_reg[inst.rd as usize] = ((long_result >> 64) & 0xffffffffffffffff) as i64; machine.int_reg.set_reg(inst.rd as usize, ((long_result >> 64) & 0xffffffffffffffff) as i64);
}, },
RISCV_OP_M_DIV => { RISCV_OP_M_DIV => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] / machine.int_reg[inst.rs2 as usize]; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) / machine.int_reg.get_reg(inst.rs2 as usize));
} }
_ => { _ => {
panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n"); panic!("RISCV_OP : funct7 = 1 (Multiplication) :: Error\n");
@ -354,42 +346,42 @@ impl Machine {
match inst.funct3 { match inst.funct3 {
RISCV_OP_ADD => { RISCV_OP_ADD => {
if inst.funct7 == RISCV_OP_ADD_ADD { if inst.funct7 == RISCV_OP_ADD_ADD {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + machine.int_reg[inst.rs2 as usize]; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + machine.int_reg.get_reg(inst.rs2 as usize));
} else { } else {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] - machine.int_reg[inst.rs2 as usize]; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) - machine.int_reg.get_reg(inst.rs2 as usize));
} }
}, },
RISCV_OP_SLL => { RISCV_OP_SLL => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << (machine.int_reg[inst.rs2 as usize] & 0x3f); machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << (machine.int_reg.get_reg(inst.rs2 as usize) & 0x3f));
}, },
RISCV_OP_SLT => { RISCV_OP_SLT => {
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
machine.int_reg[inst.rd as usize] = 1; machine.int_reg.set_reg(inst.rd as usize, 1);
} else { } else {
machine.int_reg[inst.rd as usize] = 0; machine.int_reg.set_reg(inst.rd as usize, 0);
} }
}, },
RISCV_OP_SLTU => { RISCV_OP_SLTU => {
unsigned_reg1 = machine.int_reg[inst.rs1 as usize] as u64; unsigned_reg1 = machine.int_reg.get_reg(inst.rs1 as usize) as u64;
unsigned_reg2 = machine.int_reg[inst.rs2 as usize] as u64; unsigned_reg2 = machine.int_reg.get_reg(inst.rs2 as usize) as u64;
if unsigned_reg1 < unsigned_reg2 { if unsigned_reg1 < unsigned_reg2 {
machine.int_reg[inst.rd as usize] = 1; machine.int_reg.set_reg(inst.rd as usize, 1);
} else { } else {
machine.int_reg[inst.rd as usize] = 0; machine.int_reg.set_reg(inst.rd as usize, 0);
} }
}, },
RISCV_OP_XOR => { RISCV_OP_XOR => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ machine.int_reg[inst.rs2 as usize]; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ machine.int_reg.get_reg(inst.rs2 as usize));
}, },
RISCV_OP_SR => { RISCV_OP_SR => {
// RISCV_OP_SR_SRL inaccessible // RISCV_OP_SR_SRL inaccessible
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> (machine.int_reg[inst.rs2 as usize] & 0x3f); machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) >> machine.int_reg.get_reg(inst.rs2 as usize));
}, },
RISCV_OP_OR => { RISCV_OP_OR => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | machine.int_reg[inst.rs2 as usize]; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | machine.int_reg.get_reg(inst.rs2 as usize));
}, },
RISCV_OP_AND => { RISCV_OP_AND => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & machine.int_reg[inst.rs2 as usize]; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & machine.int_reg.get_reg(inst.rs2 as usize));
}, },
_ => { _ => {
panic!("RISCV_OP undefined case\n"); panic!("RISCV_OP undefined case\n");
@ -401,53 +393,53 @@ impl Machine {
// Treatment for: OPW INSTRUCTIONS // Treatment for: OPW INSTRUCTIONS
RISCV_OPW => { RISCV_OPW => {
if inst.funct7 == 1 { if inst.funct7 == 1 {
let local_data_a = machine.int_reg[inst.rs1 as usize] & 0xffffffff; let local_data_a = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff;
let local_data_b = machine.int_reg[inst.rs2 as usize] & 0xffffffff; let local_data_b = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff;
let local_data_a_unsigned = machine.int_reg[inst.rs1 as usize] & 0xffffffff; let local_data_a_unsigned = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff;
let local_data_b_unsigned = machine.int_reg[inst.rs2 as usize] & 0xffffffff; let local_data_b_unsigned = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff;
// Match case for multiplication operations (in standard extension RV32M) // Match case for multiplication operations (in standard extension RV32M)
match inst.funct3 { match inst.funct3 {
RISCV_OPW_M_MULW => { RISCV_OPW_M_MULW => {
machine.int_reg[inst.rd as usize] = local_data_a * local_data_b; machine.int_reg.set_reg(inst.rd as usize, local_data_a * local_data_b);
}, },
RISCV_OPW_M_DIVW => { RISCV_OPW_M_DIVW => {
machine.int_reg[inst.rd as usize] = local_data_a / local_data_b; machine.int_reg.set_reg(inst.rd as usize, local_data_a / local_data_b);
}, },
RISCV_OPW_M_DIVUW => { RISCV_OPW_M_DIVUW => {
machine.int_reg[inst.rd as usize] = local_data_a_unsigned / local_data_b_unsigned; machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned / local_data_b_unsigned);
}, },
RISCV_OPW_M_REMW => { RISCV_OPW_M_REMW => {
machine.int_reg[inst.rd as usize] = local_data_a % local_data_b; machine.int_reg.set_reg(inst.rd as usize, local_data_a % local_data_b);
}, },
RISCV_OPW_M_REMUW => { RISCV_OPW_M_REMUW => {
machine.int_reg[inst.rd as usize] = local_data_a_unsigned % local_data_b_unsigned; machine.int_reg.set_reg(inst.rd as usize, local_data_a_unsigned % local_data_b_unsigned);
}, },
_ => { _ => {
panic!("this instruction ({}) doesn't exists", inst.value); panic!("this instruction ({}) doesn't exists", inst.value);
} }
} }
} else { } else {
let local_dataa = machine.int_reg[inst.rs1 as usize] & 0xffffffff; let local_dataa = machine.int_reg.get_reg(inst.rs1 as usize) & 0xffffffff;
let local_datab = machine.int_reg[inst.rs2 as usize] & 0xffffffff; let local_datab = machine.int_reg.get_reg(inst.rs2 as usize) & 0xffffffff;
// Match case for base OP operation // Match case for base OP operation
match inst.funct3 { match inst.funct3 {
RISCV_OPW_ADDSUBW => { RISCV_OPW_ADDSUBW => {
if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW { if inst.funct7 == RISCV_OPW_ADDSUBW_ADDW {
machine.int_reg[inst.rd as usize] = local_dataa + local_datab; machine.int_reg.set_reg(inst.rd as usize, local_dataa + local_datab);
} else { // SUBW } else { // SUBW
machine.int_reg[inst.rd as usize] = local_dataa - local_datab; machine.int_reg.set_reg(inst.rd as usize, local_dataa - local_datab);
} }
}, },
RISCV_OPW_SLLW => { RISCV_OPW_SLLW => {
machine.int_reg[inst.rd as usize] = local_dataa << (local_datab & 0x1f); machine.int_reg.set_reg(inst.rd as usize, local_dataa << (local_datab & 0x1f));
}, },
RISCV_OPW_SRW => { RISCV_OPW_SRW => {
if inst.funct7 == RISCV_OPW_SRW_SRLW { if inst.funct7 == RISCV_OPW_SRW_SRLW {
machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64; machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f) & machine.shiftmask[32 + local_datab as usize] as i64);
} else { // SRAW } else { // SRAW
machine.int_reg[inst.rd as usize] = local_dataa >> (local_datab & 0x1f); machine.int_reg.set_reg(inst.rd as usize, local_dataa >> (local_datab & 0x1f));
} }
}, },
_ => { _ => {

2
src/simulator/mod.rs
View File

@ -167,7 +167,7 @@ pub mod global {
/// ///
/// Store doubleword (SD) (64 bits) /// Store doubleword (SD) (64 bits)
/// ///
/// `SD rs2, imm12(rs1` => `rs2 -> mem[rs1 + imm12]` /// `SD rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]`
pub const RISCV_ST_STD: u8 = 0x3; pub const RISCV_ST_STD: u8 = 0x3;
/// Type: I /// Type: I