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📝 Documentation updates for machine.rs

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This commit is contained in:
François Autin 2023-03-23 21:55:46 +01:00
parent cc6aab7c3f
commit bee0e8ce71
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GPG Key ID: 343F5D382E1DD77C
1 changed files with 18 additions and 2 deletions
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20
src/simulator/machine.rs
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@ -109,6 +109,7 @@ pub struct Machine {
impl Machine {
/// Machine constructor
pub fn init_machine() -> Machine {
let mut shiftmask : [u64 ; 64] = [0 ; 64];
let mut value : u64 = 0xffffffff;
@ -195,6 +196,11 @@ impl Machine {
};
}
/// Print the status of the machine to the standard output
///
/// ### Parameters
///
/// - **machine** the machine to get the status from
pub fn print_machine_status(machine: &mut Machine) {
println!("######### Machine status #########");
for i in (0..32).step_by(3) {
@ -213,6 +219,11 @@ impl Machine {
println!("##################################");
}
/// Get the state of the registers as a string
///
/// ### Parameters
///
/// - **machine** the machine to read the registers from
pub fn string_registers(machine: &mut Machine) -> String {
let mut s = String::from("");
for i in 0..32 {
@ -554,7 +565,8 @@ impl Machine {
} else {
machine.fp_reg.set_reg(inst.rd as usize, -local_float)
},
RISCV_FP_FSGN_JX => if (machine.fp_reg.get_reg(inst.rs2 as usize) < 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) >= 0.0) || (machine.fp_reg.get_reg(inst.rs2 as usize) >= 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) < 0.0) {
RISCV_FP_FSGN_JX => if (machine.fp_reg.get_reg(inst.rs2 as usize) < 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) >= 0.0) ||
(machine.fp_reg.get_reg(inst.rs2 as usize) >= 0.0 && machine.fp_reg.get_reg(inst.rs1 as usize) < 0.0) {
machine.fp_reg.set_reg(inst.rd as usize, -local_float)
} else {
machine.fp_reg.set_reg(inst.rd as usize, local_float)
@ -608,7 +620,7 @@ impl Machine {
/// print memory FOR DEBUG
///
/// "@"adresse [16 bytes]
/// "@"adress [16 bytes]
pub fn _print_memory(machine : &mut Machine, from: usize, to: usize) {
for i in from..to {
if i%16 == 0 {
@ -619,18 +631,22 @@ impl Machine {
println!();
}
/// Get value from int register
pub fn read_int_register(&self, index: usize) -> i64 {
self.int_reg.get_reg(index)
}
/// Get value from float register
pub fn read_fp_register(&self, index: usize) -> f32 {
self.fp_reg.get_reg(index)
}
/// Write into int register
pub fn write_int_register(&mut self, index: usize, value: i64) {
self.int_reg.set_reg(index, value);
}
/// Write info float register
pub fn write_fp_register(&mut self, index: usize, value: f32) {
self.fp_reg.set_reg(index, value);
}