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Add support for RISCV_ST instructions

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This commit is contained in:
Quentin Legot 2023-01-18 15:26:44 +01:00
parent 1701e9b7d5
commit b75c7b2d96
1 changed files with 5 additions and 6 deletions
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11
src/simulator/machine.rs
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@ -211,17 +211,16 @@ impl Machine {
RISCV_ST => { RISCV_ST => {
match inst.funct3 { match inst.funct3 {
RISCV_ST_STB => { RISCV_ST_STB => {
Self::write_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); // Possible bugs à cause du cast ici
todo!("Write memory here");
}, },
RISCV_ST_STH => { RISCV_ST_STH => {
todo!("Write memory here"); Self::write_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64);
}, },
RISCV_ST_STW => { RISCV_ST_STW => {
todo!("Write memory here"); Self::write_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64);
}, },
RISCV_ST_STD => { RISCV_ST_STD => {
todo!("Write memory here"); Self::write_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64);
}, },
_ => { _ => {
panic!("In ST switch case, this should never happen... Instr was {}", inst.value); panic!("In ST switch case, this should never happen... Instr was {}", inst.value);
@ -257,7 +256,7 @@ impl Machine {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt; machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] >> inst.shamt;
} }
} }
_ => { panic!("{} inconnu", inst.funct3); } _ => { panic!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value); }
} }
}, },