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debug loader

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This commit is contained in:
Samy Solhi
2023-02-15 18:09:18 +01:00
parent 6c08ed24b1
commit 82c9282f0e
4 changed files with 46 additions and 17 deletions
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34
src/simulator/machine.rs
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@ -183,13 +183,14 @@ impl Machine {
println!("ERROR : number max of instructions rushed");
return ;
}
let mut val: [u8; 8] = [0; 8];
for i in 0..8 {
let mut val: [u8; 4] = [0; 4];
for i in 0..4 {
val[i] = machine.main_memory[machine.pc as usize + i];
}
let val = u64::from_le_bytes(val);
let inst : Instruction = decode(val);
let val = u32::from_be_bytes(val);
println!("{:x}", val);
let inst : Instruction = decode(val as u64);
match inst.opcode {
@ -197,11 +198,11 @@ impl Machine {
machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64);
},
RISCV_AUIPC => {
machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 8 + inst.imm31_12 as i64);
machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64);
},
RISCV_JAL => {
machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64);
machine.pc += inst.imm21_1_signed as u64 - 8;
machine.pc += inst.imm21_1_signed as u64 - 4;
},
RISCV_JALR => {
let tmp = machine.pc;
@ -215,32 +216,32 @@ impl Machine {
match inst.funct3 {
RISCV_BR_BEQ => {
if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 8;
machine.pc += inst.imm13_signed as u64 - 4;
}
},
RISCV_BR_BNE => {
if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 8;
machine.pc += inst.imm13_signed as u64 - 4;
}
},
RISCV_BR_BLT => {
if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 8;
machine.pc += inst.imm13_signed as u64 - 4;
}
},
RISCV_BR_BGE => {
if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 8;
machine.pc += inst.imm13_signed as u64 - 4;
}
},
RISCV_BR_BLTU => {
if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 8;
machine.pc += inst.imm13_signed as u64 - 4;
}
},
RISCV_BR_BGEU => {
if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 8;
machine.pc += inst.imm13_signed as u64 - 4;
}
},
_ => {
@ -602,10 +603,10 @@ impl Machine {
}
}
}
_ => { panic!("{} opcode non géré", inst.opcode)},
_ => { panic!("{:x} opcode non géré pc : {:x}", inst.opcode, machine.pc)},
}
machine.pc += 8;
machine.pc += 4; // Possible bug avec jump
}
}
@ -628,5 +629,10 @@ impl Machine {
Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150);
assert_eq!(43, m.main_memory[6]);
assert_eq!(150, m.main_memory[7]);
Machine::write_memory(&mut m, 4, 8, (52 << 24) + (20 << 16) + (43 << 8) + 150);
assert_eq!(52, m.main_memory[8]);
assert_eq!(20, m.main_memory[9]);
assert_eq!(43, m.main_memory[10]);
assert_eq!(150, m.main_memory[11]);
}
}