diff --git a/src/main.rs b/src/main.rs
index 4acaaf7..46ca3ff 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -1,14 +1,21 @@
 mod simulator;
 
 use simulator::machine::Machine;
+use simulator::loader;
 
 fn main() {
-    let mut m = Machine::_init_machine();
+
+    let mut m = loader::load("test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex", 4);
+
+    Machine::run(m);
+
+    /*let mut m = Machine::_init_machine();
     m.main_memory[4] = 43;
     m.main_memory[5] = 150;
     let a : u8 = 128;
     let b : i8 = a as i8;
     let c : u8 = b as u8;
     println!("aaa {c}");
-    println!("read_memory : {}", Machine::read_memory(&mut m, 2, 4));
-}
+    println!("read_memory : {}", Machine::read_memory(&mut m, 2, 4));*/
+
+}
\ No newline at end of file
diff --git a/src/simulator/loader.rs b/src/simulator/loader.rs
index 0391aed..5659003 100644
--- a/src/simulator/loader.rs
+++ b/src/simulator/loader.rs
@@ -29,5 +29,6 @@ pub fn load(path : &str, instruction_size: i32) -> Machine {
             _ => panic!()
         }
     }
+    println!("{:x}", Machine::read_memory(& mut machine, 4, 0));
     machine
 }
\ No newline at end of file
diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs
index f3f635b..c088af5 100644
--- a/src/simulator/machine.rs
+++ b/src/simulator/machine.rs
@@ -183,13 +183,14 @@ impl Machine {
 			println!("ERROR : number max of instructions rushed");
 			return ;
 		}
-		let mut val: [u8; 8] = [0; 8];
-		for i in 0..8 {
+		let mut val: [u8; 4] = [0; 4];
+		for i in 0..4 {
 			val[i] = machine.main_memory[machine.pc as usize + i];
 		}
 
-		let val = u64::from_le_bytes(val);
-		let inst : Instruction = decode(val);
+		let val = u32::from_be_bytes(val);
+		println!("{:x}", val);
+		let inst : Instruction = decode(val as u64);
 		
 		
 		match inst.opcode {
@@ -197,11 +198,11 @@ impl Machine {
 				machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64);
 			},
 			RISCV_AUIPC => {
-				machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 8 + inst.imm31_12 as i64);
+				machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64);
 			},
 			RISCV_JAL => {
 				machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64);
-				machine.pc += inst.imm21_1_signed as u64 - 8;
+				machine.pc += inst.imm21_1_signed as u64 - 4;
 			},
 			RISCV_JALR => {
 				let tmp = machine.pc;
@@ -215,32 +216,32 @@ impl Machine {
 				match inst.funct3 {
 					RISCV_BR_BEQ => {
 						if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) {
-							machine.pc += inst.imm13_signed as u64 - 8;
+							machine.pc += inst.imm13_signed as u64 - 4;
 						}
 					},
 					RISCV_BR_BNE => {
 						if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) {
-							machine.pc += inst.imm13_signed as u64 - 8;
+							machine.pc += inst.imm13_signed as u64 - 4;
 						}
 					},
 					RISCV_BR_BLT => {
 						if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
-							machine.pc += inst.imm13_signed as u64 - 8;
+							machine.pc += inst.imm13_signed as u64 - 4;
 						}
 					},
 					RISCV_BR_BGE => {
 						if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
-							machine.pc += inst.imm13_signed as u64 - 8;
+							machine.pc += inst.imm13_signed as u64 - 4;
 						}
 					},
 					RISCV_BR_BLTU => {
 						if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
-							machine.pc += inst.imm13_signed as u64 - 8;
+							machine.pc += inst.imm13_signed as u64 - 4;
 						}
 					},
 					RISCV_BR_BGEU => {
 						if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
-							machine.pc += inst.imm13_signed as u64 - 8;
+							machine.pc += inst.imm13_signed as u64 - 4;
 						}
 					},
 					_ => {
@@ -602,10 +603,10 @@ impl Machine {
 					}
 				}
 			}
-			_ => { panic!("{} opcode non géré", inst.opcode)},
+			_ => { panic!("{:x} opcode non géré  pc : {:x}", inst.opcode, machine.pc)},
 		}
 
-		machine.pc += 8;
+		machine.pc += 4; // Possible bug avec jump
 
 	}
 }
@@ -628,5 +629,10 @@ impl Machine {
 		Machine::write_memory(&mut m, 2, 6, (43 << 8) + 150);
 		assert_eq!(43, m.main_memory[6]);
 		assert_eq!(150, m.main_memory[7]);
+		Machine::write_memory(&mut m, 4, 8, (52 << 24) + (20 << 16) + (43 << 8) + 150);
+		assert_eq!(52, m.main_memory[8]);
+		assert_eq!(20, m.main_memory[9]);
+		assert_eq!(43, m.main_memory[10]);
+		assert_eq!(150, m.main_memory[11]);
 	}
 }
diff --git a/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex b/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex
new file mode 100644
index 0000000..d5a8502
--- /dev/null
+++ b/test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.hex
@@ -0,0 +1,15 @@
+fe010113
+00813c23
+02010413
+fe042623
+00100793
+fef42423
+fec42783
+00078713
+fe842783
+00f707bb
+fef42623
+00000013
+01813403
+02010113
+00008067
\ No newline at end of file