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♻️ Implement From<&str> and From<String> traits to MachineError, and simplified opiw_instruction

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This commit is contained in:
François Autin 2023-03-27 15:56:23 +02:00
parent 2162232199
commit 7f37965ed4
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GPG Key ID: 343F5D382E1DD77C
2 changed files with 25 additions and 25 deletions
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14
src/simulator/error.rs
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@ -14,7 +14,7 @@
//! }
//! ```
use std::fmt;
use std::fmt::{self, Error};
/// Machine Error
/// This error serves as a specific exception handler for the Machine struct
@ -42,3 +42,15 @@ impl fmt::Display for MachineError {
}
}
impl From<&str> for MachineError {
fn from(value: &str) -> Self {
MachineError { message: value.to_string() }
}
}
impl From<String> for MachineError {
fn from(value: String) -> Self {
MachineError { message: value }
}
}

34
src/simulator/machine.rs
View File

@ -299,10 +299,10 @@ impl Machine {
RISCV_FP => self.fp_instruction(inst),
// Treatment for: SYSTEM CALLS
RISCV_SYSTEM => Err(MachineError::new(format!("{:x}: System opcode\npc: {:x}", inst.opcode, self.pc).as_str())),
RISCV_SYSTEM => Err(format!("{:x}: System opcode\npc: {:x}", inst.opcode, self.pc))?,
// Default case
_ => Err(MachineError::new(format!("{:x}: Unknown opcode\npc: {:x}", inst.opcode, self.pc).as_str()))
_ => Err(format!("{:x}: Unknown opcode\npc: {:x}", inst.opcode, self.pc))?
}
}
@ -337,7 +337,7 @@ impl Machine {
RISCV_LD_LH | RISCV_LD_LHU => set_reg(inst.rd, 2),
RISCV_LD_LW | RISCV_LD_LWU => set_reg(inst.rd, 4),
RISCV_LD_LD => set_reg(inst.rd, 8),
_ => Err(MachineError::new(format!("In LD switch case, this should never happen... Instr was {}", inst.value).as_str()))
_ => Err(format!("In LD switch case, this should never happen... Instr was {}", inst.value).as_str())?
}
}
@ -356,7 +356,7 @@ impl Machine {
RISCV_ST_STH => store(2),
RISCV_ST_STW => store(4),
RISCV_ST_STD => store(8),
_ => Err(MachineError::new(format!("In ST switch case, this should never happen... Instr was {}", inst.value).as_str()))
_ => Err(format!("In ST switch case, this should never happen... Instr was {}", inst.value).as_str())?
}
}
@ -381,7 +381,7 @@ impl Machine {
} else {
compute(&core::ops::Shr::shr, rs1, shamt)
}
_ => Err(MachineError::new(format!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value).as_str()))
_ => Err(format!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value))?
}
}
@ -449,25 +449,13 @@ impl Machine {
/// Exectutes simple RISC-V *iw instructions on the machine
fn opiw_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
let local_data = self.int_reg.get_reg(inst.rs1);
match inst.funct3 {
RISCV_OPIW_ADDIW => {
let result = local_data + inst.imm12_I_signed as i64;
self.int_reg.set_reg(inst.rd, result)
},
RISCV_OPIW_SLLIW => {
let result = local_data << inst.shamt;
self.int_reg.set_reg(inst.rd, result)
},
RISCV_OPIW_SRW => {
let result = if inst.funct7 == RISCV_OPIW_SRW_SRLIW {
(local_data >> inst.shamt) & self.shiftmask[32 + inst.shamt as usize] as i64
} else { // SRAIW
local_data >> inst.shamt
let result = match inst.funct3 {
RISCV_OPIW_ADDIW => local_data + inst.imm12_I_signed as i64,
RISCV_OPIW_SLLIW => local_data << inst.shamt,
RISCV_OPIW_SRW => (local_data >> inst.shamt) & if inst.funct7 == RISCV_OPIW_SRW_SRLIW { self.shiftmask[32 + inst.shamt as usize] as i64 } else { 1 },
_ => Err("In OPI switch case, this should never happen... Instr was {}\n")?,
};
self.int_reg.set_reg(inst.rd, result)
},
_ => panic!("In OPI switch case, this should never happen... Instr was {}\n", inst.value),
}
self.int_reg.set_reg(inst.rd, result);
Ok(())
}