From 7f37965ed47f89df118a413353149d5303984af2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Autin?= Date: Mon, 27 Mar 2023 15:56:23 +0200 Subject: [PATCH] :recycle: Implement From<&str> and From traits to MachineError, and simplified opiw_instruction --- src/simulator/error.rs | 14 +++++++++++++- src/simulator/machine.rs | 36 ++++++++++++------------------------ 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/src/simulator/error.rs b/src/simulator/error.rs index 3d922a9..6b7c515 100644 --- a/src/simulator/error.rs +++ b/src/simulator/error.rs @@ -14,7 +14,7 @@ //! } //! ``` -use std::fmt; +use std::fmt::{self, Error}; /// Machine Error /// This error serves as a specific exception handler for the Machine struct @@ -41,4 +41,16 @@ impl fmt::Display for MachineError { write!(f, "Machine error: {}", &self.message) } +} + +impl From<&str> for MachineError { + fn from(value: &str) -> Self { + MachineError { message: value.to_string() } + } +} + +impl From for MachineError { + fn from(value: String) -> Self { + MachineError { message: value } + } } \ No newline at end of file diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index b9aa48e..55a31e5 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -299,10 +299,10 @@ impl Machine { RISCV_FP => self.fp_instruction(inst), // Treatment for: SYSTEM CALLS - RISCV_SYSTEM => Err(MachineError::new(format!("{:x}: System opcode\npc: {:x}", inst.opcode, self.pc).as_str())), + RISCV_SYSTEM => Err(format!("{:x}: System opcode\npc: {:x}", inst.opcode, self.pc))?, // Default case - _ => Err(MachineError::new(format!("{:x}: Unknown opcode\npc: {:x}", inst.opcode, self.pc).as_str())) + _ => Err(format!("{:x}: Unknown opcode\npc: {:x}", inst.opcode, self.pc))? } } @@ -337,7 +337,7 @@ impl Machine { RISCV_LD_LH | RISCV_LD_LHU => set_reg(inst.rd, 2), RISCV_LD_LW | RISCV_LD_LWU => set_reg(inst.rd, 4), RISCV_LD_LD => set_reg(inst.rd, 8), - _ => Err(MachineError::new(format!("In LD switch case, this should never happen... Instr was {}", inst.value).as_str())) + _ => Err(format!("In LD switch case, this should never happen... Instr was {}", inst.value).as_str())? } } @@ -356,7 +356,7 @@ impl Machine { RISCV_ST_STH => store(2), RISCV_ST_STW => store(4), RISCV_ST_STD => store(8), - _ => Err(MachineError::new(format!("In ST switch case, this should never happen... Instr was {}", inst.value).as_str())) + _ => Err(format!("In ST switch case, this should never happen... Instr was {}", inst.value).as_str())? } } @@ -381,7 +381,7 @@ impl Machine { } else { compute(&core::ops::Shr::shr, rs1, shamt) } - _ => Err(MachineError::new(format!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value).as_str())) + _ => Err(format!("In OPI switch case, this should never happen... Instr was %x\n {}", inst.value))? } } @@ -449,25 +449,13 @@ impl Machine { /// Exectutes simple RISC-V *iw instructions on the machine fn opiw_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> { let local_data = self.int_reg.get_reg(inst.rs1); - match inst.funct3 { - RISCV_OPIW_ADDIW => { - let result = local_data + inst.imm12_I_signed as i64; - self.int_reg.set_reg(inst.rd, result) - }, - RISCV_OPIW_SLLIW => { - let result = local_data << inst.shamt; - self.int_reg.set_reg(inst.rd, result) - }, - RISCV_OPIW_SRW => { - let result = if inst.funct7 == RISCV_OPIW_SRW_SRLIW { - (local_data >> inst.shamt) & self.shiftmask[32 + inst.shamt as usize] as i64 - } else { // SRAIW - local_data >> inst.shamt - }; - self.int_reg.set_reg(inst.rd, result) - }, - _ => panic!("In OPI switch case, this should never happen... Instr was {}\n", inst.value), - } + let result = match inst.funct3 { + RISCV_OPIW_ADDIW => local_data + inst.imm12_I_signed as i64, + RISCV_OPIW_SLLIW => local_data << inst.shamt, + RISCV_OPIW_SRW => (local_data >> inst.shamt) & if inst.funct7 == RISCV_OPIW_SRW_SRLIW { self.shiftmask[32 + inst.shamt as usize] as i64 } else { 1 }, + _ => Err("In OPI switch case, this should never happen... Instr was {}\n")?, + }; + self.int_reg.set_reg(inst.rd, result); Ok(()) }