📝 Documentation updates

This commit is contained in:
François Autin 2023-03-24 19:02:50 +01:00
parent 4e90d9fef7
commit 7ed53261a0
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4 changed files with 39 additions and 12 deletions

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@ -1,3 +1,19 @@
//! # Error
//!
//! This module contains the definition of the MachineError struct,
//! for error management in the Machine module.
//!
//! Basic usage:
//!
//! ```
//! fn example(x: bool) -> Result<(), MachineError> {
//! match x {
//! true => Ok(()),
//! _ => Err(MachineError::new("Machine failed because of ..."));
//! }
//! }
//! ```
use std::fmt; use std::fmt;
/// Machine Error /// Machine Error

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@ -1,3 +1,16 @@
//! # Machine
//!
//! This module contains a RISC-V simulator.
//! It supports the base instruction set along
//! with 32bit floating point operations.
//!
//! Basic usage:
//!
//! ```
//! let mut machine = Machine::init_machine();
//! machine.run();
//! ```
use std::{ use std::{
io::Write, io::Write,
fs::File fs::File

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@ -9,6 +9,7 @@ pub mod translationtable;
pub mod mmu; pub mod mmu;
pub mod register; pub mod register;
/// Definition of global constants
pub mod global { pub mod global {
#![allow(dead_code)] #![allow(dead_code)]
@ -54,15 +55,15 @@ pub mod global {
/// ///
/// See func3 to know the type of instruction (LD, LW, LH, LB, LWU, LHU, LBU) /// See func3 to know the type of instruction (LD, LW, LH, LB, LWU, LHU, LBU)
pub const RISCV_LD: u8 = 0x3; pub const RISCV_LD: u8 = 0x3;
// Store instructions /// Store instructions
pub const RISCV_ST: u8 = 0x23; pub const RISCV_ST: u8 = 0x23;
// immediate Arithmetic operations /// immediate Arithmetic operations
pub const RISCV_OPI: u8 = 0x13; pub const RISCV_OPI: u8 = 0x13;
// Arithmetic operations /// Arithmetic operations
pub const RISCV_OP: u8 = 0x33; pub const RISCV_OP: u8 = 0x33;
/// Immediate arithmetic operations for rv64i /// Immediate arithmetic operations for rv64i
pub const RISCV_OPIW: u8 = 0x1b; pub const RISCV_OPIW: u8 = 0x1b;
// Arithmetic operations for rv64i /// Arithmetic operations for rv64i
pub const RISCV_OPW: u8 = 0x3b; pub const RISCV_OPW: u8 = 0x3b;
/// Type: B /// Type: B

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@ -1,5 +1,9 @@
use crate::simulator::machine::{NUM_FP_REGS, NUM_INT_REGS}; //! # Register
//!
//! This mod contains the definition of the Register structs
//! for use within the Machine module.
use crate::simulator::machine::{NUM_FP_REGS, NUM_INT_REGS};
use std::ops::{Add, Sub}; use std::ops::{Add, Sub};
pub trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {} pub trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {}
@ -16,7 +20,6 @@ pub struct Register<U: RegisterNum> {
} }
impl<U: RegisterNum> Register<U> { impl<U: RegisterNum> Register<U> {
/// Returns the current value held in register *position* /// Returns the current value held in register *position*
pub fn get_reg(&self, position: u8) -> U { pub fn get_reg(&self, position: u8) -> U {
self.register[position as usize] self.register[position as usize]
@ -29,28 +32,22 @@ impl<U: RegisterNum> Register<U> {
pub fn set_reg(&mut self, position: u8, value: U) { pub fn set_reg(&mut self, position: u8, value: U) {
if position != 0 { self.register[position as usize] = value; } if position != 0 { self.register[position as usize] = value; }
} }
} }
impl Register<i64> { impl Register<i64> {
/// i64 register constructor /// i64 register constructor
pub fn init() -> Register<i64> { pub fn init() -> Register<i64> {
Register { Register {
register: [0i64; NUM_INT_REGS] register: [0i64; NUM_INT_REGS]
} }
} }
} }
impl Register<f32> { impl Register<f32> {
/// f32 register constructor /// f32 register constructor
pub fn init() -> Register<f32> { pub fn init() -> Register<f32> {
Register { Register {
register: [0f32; NUM_FP_REGS] register: [0f32; NUM_FP_REGS]
} }
} }
} }