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Convert some fp reg from array to struct call

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This commit is contained in:
Quentin Legot 2023-02-01 17:26:34 +01:00
parent d04072c89a
commit 658502d353
1 changed files with 7 additions and 5 deletions
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12
src/simulator/machine.rs
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@ -59,6 +59,7 @@ impl Register<f32> {
pub struct Machine {
pub pc : u64,
pub int_reg : Register<i64>,
pub fp_reg : Register<f32>,
pub instructions : [u64 ; 100],
pub main_memory : [u8 ; MEM_SIZE],
pub shiftmask : [u64 ; 64]
@ -86,6 +87,7 @@ impl Machine {
pc : 0,
instructions : [0 ; 100],
int_reg : Register::<i64>::init(),
fp_reg: Register::<f32>::init(),
main_memory : [0 ; MEM_SIZE],
shiftmask
}
@ -453,19 +455,19 @@ impl Machine {
RISCV_FP => {
match inst.funct7 {
RISCV_FP_ADD => {
machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] + machine.fp_reg[inst.rs2 as usize];
machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) + machine.fp_reg.get_reg(inst.rs2 as usize));
},
RISCV_FP_SUB => {
machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] - machine.fp_reg[inst.rs2 as usize];
machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) - machine.fp_reg.get_reg(inst.rs2 as usize));
},
RISCV_FP_MUL => {
machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] * machine.fp_reg[inst.rs2 as usize];
machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) * machine.fp_reg.get_reg(inst.rs2 as usize));
},
RISCV_FP_DIV => {
machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize] / machine.fp_reg[inst.rs2 as usize];
machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize) / machine.fp_reg.get_reg(inst.rs2 as usize));
},
RISCV_FP_SQRT => {
machine.fp_reg[inst.rd as usize] = machine.fp_reg[inst.rs1 as usize].sqrt();
machine.fp_reg.set_reg(inst.rd as usize, machine.fp_reg.get_reg(inst.rs1 as usize).sqrt());
},
RISCV_FP_FSGN => {
let local_float = machine.fp_reg[inst.rs1 as usize];