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Merge branch 'decode_print' of gitlab.istic.univ-rennes1.fr:simpleos/burritos into decode_print

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This commit is contained in:
Rémi Rativel 2023-02-15 16:14:45 +01:00
commit 4a201268e7
4 changed files with 44 additions and 38 deletions
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12
src/simulator/mem_cmp.rs
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@ -94,7 +94,10 @@ impl Mem_Checker{
pub fn from(path: &String) -> Mem_Checker { pub fn from(path: &String) -> Mem_Checker {
let file = fs::File::open("test_file_section.txt").expect("Wrong filename"); let file = fs::File::open("test_file_section.txt").expect("Wrong filename");
let reader = io::BufReader::new(file); let reader = io::BufReader::new(&file);
let reader2 = io::BufReader::new(&file);
let lines = reader.lines();
let length = reader2.lines().count();
let mut pc: usize = 0; let mut pc: usize = 0;
let mut sp: usize = 0; let mut sp: usize = 0;
@ -103,15 +106,15 @@ impl Mem_Checker{
let mut tmp_addr_str: String = String::new(); let mut tmp_addr_str: String = String::new();
let mut tmp_len_str: String = String::new(); let mut tmp_len_str: String = String::new();
for (i,line) in reader.lines().enumerate() { for (i,line) in lines.enumerate() {
let current_line = line.unwrap(); let current_line = line.unwrap();
if i == current_line.len()-2 { if i == length-2 {
//Lecture de PC //Lecture de PC
pc = string_hex_to_usize(&current_line); pc = string_hex_to_usize(&current_line);
} }
else if i == current_line.len()-1 { else if i == length-1 {
//Lecture SP //Lecture SP
sp = string_hex_to_usize(&current_line); sp = string_hex_to_usize(&current_line);
} }
@ -277,7 +280,6 @@ mod tests {
} }
#[test] #[test]
fn test_enum_start_at_zero(){ fn test_enum_start_at_zero(){
let v = vec![1,2,3]; let v = vec![1,2,3];

47
src/simulator/print.rs
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@ -142,79 +142,76 @@ pub fn print(ins: Instruction, pc: i32) -> String { //TODO pc should be u64
let name: &str; let name: &str;
match ins.funct7 { match ins.funct7 {
RISCV_FP_ADD => { RISCV_FP_ADD => {
name = "fadd"; format!("{}\t{}{}{}", "fadd", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_FP_SUB => { RISCV_FP_SUB => {
name = "fsub"; format!("{}\t{}{}{}", "fsub.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_FP_MUL => { RISCV_FP_MUL => {
name = "fmul"; format!("{}\t{}{}{}", "fmul.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_FP_DIV => { RISCV_FP_DIV => {
name = "fdiv"; format!("{}\t{}{}{}", "fdiv.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_FP_SQRT => { RISCV_FP_SQRT => {
name = "fsqrt"; format!("{}\t{}{}", "fsqrt.s", REG_F[rd], REG_F[rs1])
}, },
RISCV_FP_FSGN => { RISCV_FP_FSGN => {
match ins.funct3 { match ins.funct3 {
RISCV_FP_FSGN_J => { RISCV_FP_FSGN_J => {
name = "fsgnj"; format!("{}\t{}{}{}", "fsgnj.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_FP_FSGN_JN => { RISCV_FP_FSGN_JN => {
name = "fsgnn"; format!("{}\t{}{}{}", "fsgnn.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_FP_FSGN_JX => { RISCV_FP_FSGN_JX => {
name = "fsgnx"; format!("{}\t{}{}{}", "fsgnx.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
_ => name = "fsgn" _ => todo!("Unknown code")
} }
}, },
RISCV_FP_MINMAX => { RISCV_FP_MINMAX => {
if ins.funct3 == 0 { if ins.funct3 == 0 {
name = "fmin"; format!("{}\t{}{}{}", "fmin.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} else { } else {
name = "fmax"; format!("{}\t{}{}{}", "fmax.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} }
}, },
RISCV_FP_FCVTW => { RISCV_FP_FCVTW => {
if rs2 == 0 { if rs2 == 0 {
name = "fcvt.w.s"; format!("{}\t{}{}", "fcvt.w.s", REG_F[rd], REG_F[rs1])
} else { } else {
name = "fcvt.wu.s"; format!("{}\t{}{}", "fcvt.wu.s", REG_F[rd], REG_F[rs1])
} }
}, },
RISCV_FP_FMVXFCLASS => { RISCV_FP_FMVXFCLASS => {
if ins.funct3 == 0 { if ins.funct3 == 0 {
name = "fmv.x.w"; format!("{}\t{}{}", "fmv.x.w", REG_F[rd], REG_F[rs1])
} else { } else {
name = "fclass.s"; format!("{}\t{}{}", "fclass.s", REG_F[rd], REG_F[rs1])
} }
}, },
RISCV_FP_FCMP => { RISCV_FP_FCMP => {
if ins.funct3 == 0 { if ins.funct3 == 0 {
name = "fle.s"; format!("{}\t{}{}{}", "fle.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} else if ins.funct3 == 1 { } else if ins.funct3 == 1 {
name = "flt.s"; format!("{}\t{}{}{}", "flt.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} else { } else {
name = "feq.s"; format!("{}\t{}{}{}", "feq.s", REG_F[rd], REG_F[rs1], REG_F[rs2])
} }
}, },
RISCV_FP_FCVTS => { RISCV_FP_FCVTS => {
if rs2 == 0 { if rs2 == 0 {
name = "fcvt.s.w" format!("{}\t{}{}", "fcvt.s.w", REG_F[rd], REG_F[rs1])
} else { } else {
name = "fcvt.s.wu" format!("{}\t{}{}", "fcvt.s.wu", REG_F[rd], REG_F[rs1])
} }
}, },
RISCV_FP_FMVW => { RISCV_FP_FMVW => {
name = "fmv.w.x"; format!("{}\t{}{}", "fmv.w.x", REG_F[rd], REG_F[rs1])
}, },
_ => name = "todo" _ => todo!("Unknown code")
} }
format!("{}\t{}{}{}", name, REG_F[rd], REG_F[rs1], REG_F[rs2])
}, },
RISCV_SYSTEM => { RISCV_SYSTEM => {

23
test_file_section.txt
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@ -1,8 +1,15 @@
0 addi sp,sp,-32
0 sd s0,24(sp)
FF FF addi s0,sp,32
F4A12200 sw zero,-20(s0)
A0 0A li a5,1
01022B sw a5,-24(s0)
0B 0F lw a5,-20(s0)
FFACBC5CEF mv a4,a5
lw a5,-24(s0)
addw a5,a4,a5
sw a5,-20(s0)
nop
ld s0,24(sp)
addi sp,sp,32
ret

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test_programs/riscv_instructions/simple_arithmerics/unsigned_addition.o Normal file
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