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♻️ simplified store_instruction using closure

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François Autin 2023-03-25 15:43:33 +01:00
parent 651e03a446
commit 3dfeca4c42
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GPG Key ID: 343F5D382E1DD77C
1 changed files with 13 additions and 4 deletions
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17
src/simulator/machine.rs
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@ -364,13 +364,22 @@ impl Machine {
/// Executes RISC-V Store Instructions on the machine /// Executes RISC-V Store Instructions on the machine
fn store_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> { fn store_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
let mut store = |size|
self.write_memory(
size,
(self.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize,
self.int_reg.get_reg(inst.rs2) as u64
);
match inst.funct3 { match inst.funct3 {
RISCV_ST_STB => self.write_memory(1, (self.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, self.int_reg.get_reg(inst.rs2) as u64), RISCV_ST_STB => store(1),
RISCV_ST_STH => self.write_memory(2, (self.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, self.int_reg.get_reg(inst.rs2) as u64), RISCV_ST_STH => store(2),
RISCV_ST_STW => self.write_memory(4, (self.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, self.int_reg.get_reg(inst.rs2) as u64), RISCV_ST_STW => store(4),
RISCV_ST_STD => self.write_memory(8, (self.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, self.int_reg.get_reg(inst.rs2) as u64), RISCV_ST_STD => store(8),
_ => panic!("In ST switch case, this should never happen... Instr was {}", inst.value) _ => panic!("In ST switch case, this should never happen... Instr was {}", inst.value)
} }
Ok(()) Ok(())
} }