diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs
index c721876..a43b06c 100644
--- a/src/simulator/machine.rs
+++ b/src/simulator/machine.rs
@@ -364,13 +364,22 @@ impl Machine {
 
 	/// Executes RISC-V Store Instructions on the machine
 	fn store_instruction(&mut self, inst: Instruction) -> Result<(), MachineError> {
+
+		let mut store = |size|
+			self.write_memory(
+				size,
+				(self.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize,
+				self.int_reg.get_reg(inst.rs2) as u64
+			);
+
 		match inst.funct3 {
-			RISCV_ST_STB => self.write_memory(1, (self.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, self.int_reg.get_reg(inst.rs2) as u64),
-			RISCV_ST_STH => self.write_memory(2, (self.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, self.int_reg.get_reg(inst.rs2) as u64),
-			RISCV_ST_STW => self.write_memory(4, (self.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, self.int_reg.get_reg(inst.rs2) as u64),
-			RISCV_ST_STD => self.write_memory(8, (self.int_reg.get_reg(inst.rs1) + inst.imm12_S_signed as i64) as usize, self.int_reg.get_reg(inst.rs2) as u64),
+			RISCV_ST_STB => store(1),
+			RISCV_ST_STH => store(2),
+			RISCV_ST_STW => store(4),
+			RISCV_ST_STD => store(8),
 			_ => 			panic!("In ST switch case, this should never happen... Instr was {}", inst.value)
 		}
+
 		Ok(())
 	}