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Fix RISCV_LD instructions

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This commit is contained in:
Quentin Legot 2023-01-18 15:12:25 +01:00
parent 89cc9423bd
commit 1701e9b7d5
1 changed files with 8 additions and 8 deletions
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16
src/simulator/machine.rs
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@ -179,27 +179,27 @@ impl Machine {
RISCV_LD => { RISCV_LD => {
match inst.funct3 { match inst.funct3 {
RISCV_LD_LB => { RISCV_LD_LB => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
}, },
RISCV_LD_LH => { RISCV_LD_LH => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
}, },
RISCV_LD_LW => { RISCV_LD_LW => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
}, },
RISCV_LD_LD => { RISCV_LD_LD => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
}, },
// same thing three opration ? // same thing three opration ?
RISCV_LD_LBU => { RISCV_LD_LBU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
}, },
RISCV_LD_LHU => { RISCV_LD_LHU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
}, },
RISCV_LD_LWU => { RISCV_LD_LWU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64; machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
}, },
_ => { _ => {
panic!("In LD switch case, this should never happen... Instr was {}", inst.value); panic!("In LD switch case, this should never happen... Instr was {}", inst.value);
@ -211,7 +211,7 @@ impl Machine {
RISCV_ST => { RISCV_ST => {
match inst.funct3 { match inst.funct3 {
RISCV_ST_STB => { RISCV_ST_STB => {
todo!("Write memory here"); todo!("Write memory here");
}, },
RISCV_ST_STH => { RISCV_ST_STH => {