diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs
index a94492d..73fc9f3 100644
--- a/src/simulator/machine.rs
+++ b/src/simulator/machine.rs
@@ -179,27 +179,27 @@ impl Machine {
 			RISCV_LD => {
 				match inst.funct3 {
 					RISCV_LD_LB => {
-						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
 					},
 					RISCV_LD_LH => {
-						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
 					},
 					RISCV_LD_LW => {
-						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
 					},
 					RISCV_LD_LD => {
-						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
 					},
 
 					// same thing three opration ? 
 					RISCV_LD_LBU => {
-						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
 					},
 					RISCV_LD_LHU => {
-						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
 					},
 					RISCV_LD_LWU => {
-						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (inst.rs1 as i16 + inst.imm12_I_signed) as usize) as i64;
+						machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
 					},
 					_ => {
 						panic!("In LD switch case, this should never happen... Instr was {}", inst.value);
@@ -211,7 +211,7 @@ impl Machine {
 			RISCV_ST => {
 				match inst.funct3 {
 					RISCV_ST_STB => {
-						
+
 						todo!("Write memory here");
 					},
 					RISCV_ST_STH => {