Rativel/BurritOS
1
1
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Fix errors preventing compiling

Browse Source
This commit is contained in:
Quentin Legot 2023-02-01 17:10:11 +01:00
parent 2508cd408f
commit 0e89061a03
1 changed files with 10 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/simulator/machine.rs
View File

@ -5,13 +5,13 @@ use super::global::*;
/// doit disparaitre /// doit disparaitre
const MEM_SIZE : usize = 4096; const MEM_SIZE : usize = 4096;
trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {} pub trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {}
impl RegisterNum for i64 {} impl RegisterNum for i64 {}
impl RegisterNum for f32 {} impl RegisterNum for f32 {}
struct Register<U: RegisterNum> { pub struct Register<U: RegisterNum> {
register: [U; 32] register: [U; 32]
} }
@ -235,16 +235,20 @@ impl Machine {
RISCV_LD => { RISCV_LD => {
match inst.funct3 { match inst.funct3 {
RISCV_LD_LB | RISCV_LD_LBU => { RISCV_LD_LB | RISCV_LD_LBU => {
machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
machine.int_reg.set_reg(inst.rd as usize, tmp);
}, },
RISCV_LD_LH | RISCV_LD_LHU => { RISCV_LD_LH | RISCV_LD_LHU => {
machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); let tmp = Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
machine.int_reg.set_reg(inst.rd as usize, tmp);
}, },
RISCV_LD_LW | RISCV_LD_LWU => { RISCV_LD_LW | RISCV_LD_LWU => {
machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); let tmp = Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
machine.int_reg.set_reg(inst.rd as usize, tmp);
}, },
RISCV_LD_LD => { RISCV_LD_LD => {
machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
machine.int_reg.set_reg(inst.rd as usize, tmp);
}, },
_ => { _ => {
panic!("In LD switch case, this should never happen... Instr was {}", inst.value); panic!("In LD switch case, this should never happen... Instr was {}", inst.value);