diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs
index 2c6f035..b22d576 100644
--- a/src/simulator/machine.rs
+++ b/src/simulator/machine.rs
@@ -5,13 +5,13 @@ use super::global::*;
 /// doit disparaitre
 const MEM_SIZE : usize = 4096;
 
-trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {}
+pub trait RegisterNum: Add<Output=Self> + Sub<Output=Self> + PartialEq + Copy {}
 
 impl RegisterNum for i64 {}
 
 impl RegisterNum for f32 {}
 
-struct Register<U: RegisterNum> {
+pub struct Register<U: RegisterNum> {
 	register: [U; 32]
 }
 
@@ -235,16 +235,20 @@ impl Machine {
 			RISCV_LD => {
 				match inst.funct3 {
 					RISCV_LD_LB | RISCV_LD_LBU => {
-						machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64);
+						let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
+						machine.int_reg.set_reg(inst.rd as usize, tmp);
 					},
 					RISCV_LD_LH | RISCV_LD_LHU => {
-						machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64);
+						let tmp = Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
+						machine.int_reg.set_reg(inst.rd as usize, tmp);
 					},
 					RISCV_LD_LW | RISCV_LD_LWU => {
-						machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64);
+						let tmp = Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
+						machine.int_reg.set_reg(inst.rd as usize, tmp);
 					},
 					RISCV_LD_LD => {
-						machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64);
+						let tmp = Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64;
+						machine.int_reg.set_reg(inst.rd as usize, tmp);
 					},
 					_ => {
 						panic!("In LD switch case, this should never happen... Instr was {}", inst.value);