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Using a struct for registers instead of an array

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This commit is contained in:
Quentin Legot 2023-02-01 16:39:40 +01:00
parent dd90f0cea7
commit 069a8e5741
2 changed files with 31 additions and 43 deletions
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72
src/simulator/machine.rs
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@ -58,7 +58,7 @@ impl Register<f32> {
pub struct Machine { pub struct Machine {
pub pc : u64, pub pc : u64,
pub int_reg : [i64 ; 32], pub int_reg : Register<i64>,
pub instructions : [u64 ; 100], pub instructions : [u64 ; 100],
pub main_memory : [u8 ; MEM_SIZE], pub main_memory : [u8 ; MEM_SIZE],
pub shiftmask : [u64 ; 64] pub shiftmask : [u64 ; 64]
@ -85,7 +85,7 @@ impl Machine {
Machine { Machine {
pc : 0, pc : 0,
instructions : [0 ; 100], instructions : [0 ; 100],
int_reg : [0 ; 32], int_reg : Register::<i64>::init(),
main_memory : [0 ; MEM_SIZE], main_memory : [0 ; MEM_SIZE],
shiftmask shiftmask
} }
@ -175,19 +175,19 @@ impl Machine {
match inst.opcode { match inst.opcode {
RISCV_LUI => { RISCV_LUI => {
machine.int_reg[inst.rd as usize] = inst.imm31_12 as i64; machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64);
}, },
RISCV_AUIPC => { RISCV_AUIPC => {
machine.int_reg[inst.rd as usize] = machine.pc as i64 - 4 + inst.imm31_12 as i64; machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64);
}, },
RISCV_JAL => { RISCV_JAL => {
machine.int_reg[inst.rd as usize] = machine.pc as i64; machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64);
machine.pc += inst.imm21_1_signed as u64 - 4; machine.pc += inst.imm21_1_signed as u64 - 4;
}, },
RISCV_JALR => { RISCV_JALR => {
let tmp = machine.pc; let tmp = machine.pc;
machine.pc = (machine.int_reg[inst.rs1 as usize] as u64 + inst.imm12_I_signed as u64) & 0xfffffffe; machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 + inst.imm12_I_signed as u64) & 0xfffffffe;
machine.int_reg[inst.rd as usize] = tmp as i64; machine.int_reg.set_reg(inst.rd as usize, tmp as i64);
}, },
//****************************************************************************************** //******************************************************************************************
@ -195,32 +195,32 @@ impl Machine {
RISCV_BR => { RISCV_BR => {
match inst.funct3 { match inst.funct3 {
RISCV_BR_BEQ => { RISCV_BR_BEQ => {
if machine.int_reg[inst.rs1 as usize] == machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RISCV_BR_BNE => { RISCV_BR_BNE => {
if machine.int_reg[inst.rs1 as usize] != machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RISCV_BR_BLT => { RISCV_BR_BLT => {
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RISCV_BR_BGE => { RISCV_BR_BGE => {
if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RISCV_BR_BLTU => { RISCV_BR_BLTU => {
if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
RISCV_BR_BGEU => { RISCV_BR_BGEU => {
if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) {
machine.pc += inst.imm13_signed as u64 - 4; machine.pc += inst.imm13_signed as u64 - 4;
} }
}, },
@ -234,49 +234,37 @@ impl Machine {
// Treatment for: LOAD INSTRUCTIONS // Treatment for: LOAD INSTRUCTIONS
RISCV_LD => { RISCV_LD => {
match inst.funct3 { match inst.funct3 {
RISCV_LD_LB => { RISCV_LD_LB | RISCV_LD_LBU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64);
}, },
RISCV_LD_LH => { RISCV_LD_LH | RISCV_LD_LHU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64);
}, },
RISCV_LD_LW => { RISCV_LD_LW | RISCV_LD_LWU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64);
}, },
RISCV_LD_LD => { RISCV_LD_LD => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64);
},
// same thing three opration ?
RISCV_LD_LBU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
},
RISCV_LD_LHU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
},
RISCV_LD_LWU => {
machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64;
}, },
_ => { _ => {
panic!("In LD switch case, this should never happen... Instr was {}", inst.value); panic!("In LD switch case, this should never happen... Instr was {}", inst.value);
} }
} }
}, },
// store instructions // store instructions
RISCV_ST => { RISCV_ST => {
match inst.funct3 { match inst.funct3 {
RISCV_ST_STB => { RISCV_ST_STB => {
Self::write_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); // Possible bugs à cause du cast ici Self::write_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
}, },
RISCV_ST_STH => { RISCV_ST_STH => {
Self::write_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); Self::write_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
}, },
RISCV_ST_STW => { RISCV_ST_STW => {
Self::write_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); Self::write_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
}, },
RISCV_ST_STD => { RISCV_ST_STD => {
Self::write_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); Self::write_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64);
}, },
_ => { _ => {
panic!("In ST switch case, this should never happen... Instr was {}", inst.value); panic!("In ST switch case, this should never happen... Instr was {}", inst.value);
@ -288,22 +276,22 @@ impl Machine {
RISCV_OPI => { RISCV_OPI => {
match inst.funct3 { match inst.funct3 {
RISCV_OPI_ADDI => { RISCV_OPI_ADDI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64);
}, },
RISCV_OPI_SLTI => { RISCV_OPI_SLTI => {
machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64) as i64; machine.int_reg.set_reg(inst.rd as usize, if machine.int_reg.get_reg(inst.rs1 as usize) < inst.imm12_I_signed as i64 { 1 } else { 0 } );
}, },
RISCV_OPI_XORI => { RISCV_OPI_XORI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ inst.imm12_I_signed as i64);
}, },
RISCV_OPI_ORI => { RISCV_OPI_ORI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as i64; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | inst.imm12_I_signed as i64);
}, },
RISCV_OPI_ANDI => { RISCV_OPI_ANDI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as i64; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & inst.imm12_I_signed as i64);
}, },
RISCV_OPI_SLLI => { RISCV_OPI_SLLI => {
machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << inst.shamt);
}, },
RISCV_OPI_SRI => { RISCV_OPI_SRI => {
if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { if inst.funct7_smaller == RISCV_OPI_SRI_SRLI {

2
src/simulator/mod.rs
View File

@ -167,7 +167,7 @@ pub mod global {
/// ///
/// Store doubleword (SD) (64 bits) /// Store doubleword (SD) (64 bits)
/// ///
/// `SD rs2, imm12(rs1` => `rs2 -> mem[rs1 + imm12]` /// `SD rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]`
pub const RISCV_ST_STD: u8 = 0x3; pub const RISCV_ST_STD: u8 = 0x3;
/// Type: I /// Type: I