From 069a8e57414ac63fe2b9d75103f70db3a7124701 Mon Sep 17 00:00:00 2001 From: Quentin Legot Date: Wed, 1 Feb 2023 16:39:40 +0100 Subject: [PATCH] Using a struct for registers instead of an array --- src/simulator/machine.rs | 72 +++++++++++++++++----------------------- src/simulator/mod.rs | 2 +- 2 files changed, 31 insertions(+), 43 deletions(-) diff --git a/src/simulator/machine.rs b/src/simulator/machine.rs index e336842..45bafe7 100644 --- a/src/simulator/machine.rs +++ b/src/simulator/machine.rs @@ -58,7 +58,7 @@ impl Register { pub struct Machine { pub pc : u64, - pub int_reg : [i64 ; 32], + pub int_reg : Register, pub instructions : [u64 ; 100], pub main_memory : [u8 ; MEM_SIZE], pub shiftmask : [u64 ; 64] @@ -85,7 +85,7 @@ impl Machine { Machine { pc : 0, instructions : [0 ; 100], - int_reg : [0 ; 32], + int_reg : Register::::init(), main_memory : [0 ; MEM_SIZE], shiftmask } @@ -175,19 +175,19 @@ impl Machine { match inst.opcode { RISCV_LUI => { - machine.int_reg[inst.rd as usize] = inst.imm31_12 as i64; + machine.int_reg.set_reg(inst.rd as usize, inst.imm31_12 as i64); }, RISCV_AUIPC => { - machine.int_reg[inst.rd as usize] = machine.pc as i64 - 4 + inst.imm31_12 as i64; + machine.int_reg.set_reg(inst.rd as usize,machine.pc as i64 - 4 + inst.imm31_12 as i64); }, RISCV_JAL => { - machine.int_reg[inst.rd as usize] = machine.pc as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.pc as i64); machine.pc += inst.imm21_1_signed as u64 - 4; }, RISCV_JALR => { let tmp = machine.pc; - machine.pc = (machine.int_reg[inst.rs1 as usize] as u64 + inst.imm12_I_signed as u64) & 0xfffffffe; - machine.int_reg[inst.rd as usize] = tmp as i64; + machine.pc = (machine.int_reg.get_reg(inst.rs1 as usize) as u64 + inst.imm12_I_signed as u64) & 0xfffffffe; + machine.int_reg.set_reg(inst.rd as usize, tmp as i64); }, //****************************************************************************************** @@ -195,32 +195,32 @@ impl Machine { RISCV_BR => { match inst.funct3 { RISCV_BR_BEQ => { - if machine.int_reg[inst.rs1 as usize] == machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) == machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BNE => { - if machine.int_reg[inst.rs1 as usize] != machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) != machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BLT => { - if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BGE => { - if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BLTU => { - if machine.int_reg[inst.rs1 as usize] < machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) < machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, RISCV_BR_BGEU => { - if machine.int_reg[inst.rs1 as usize] >= machine.int_reg[inst.rs2 as usize] { + if machine.int_reg.get_reg(inst.rs1 as usize) >= machine.int_reg.get_reg(inst.rs2 as usize) { machine.pc += inst.imm13_signed as u64 - 4; } }, @@ -234,49 +234,37 @@ impl Machine { // Treatment for: LOAD INSTRUCTIONS RISCV_LD => { match inst.funct3 { - RISCV_LD_LB => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; + RISCV_LD_LB | RISCV_LD_LBU => { + machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); }, - RISCV_LD_LH => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; + RISCV_LD_LH | RISCV_LD_LHU => { + machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); }, - RISCV_LD_LW => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; + RISCV_LD_LW | RISCV_LD_LWU => { + machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); }, RISCV_LD_LD => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; - }, - - // same thing three opration ? - RISCV_LD_LBU => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; - }, - RISCV_LD_LHU => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; - }, - RISCV_LD_LWU => { - machine.int_reg[inst.rd as usize] = Self::read_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64) as usize) as i64; + machine.int_reg.set_reg(inst.rd as usize, Self::read_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64) as usize) as i64); }, _ => { panic!("In LD switch case, this should never happen... Instr was {}", inst.value); } } }, - // store instructions RISCV_ST => { match inst.funct3 { RISCV_ST_STB => { - Self::write_memory(machine, 1, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); // Possible bugs à cause du cast ici + Self::write_memory(machine, 1, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64); }, RISCV_ST_STH => { - Self::write_memory(machine, 2, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); + Self::write_memory(machine, 2, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64); }, RISCV_ST_STW => { - Self::write_memory(machine, 4, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); + Self::write_memory(machine, 4, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64); }, RISCV_ST_STD => { - Self::write_memory(machine, 8, (machine.int_reg[inst.rs1 as usize] + inst.imm12_S_signed as i64) as usize, machine.int_reg[inst.rs2 as usize] as u64); + Self::write_memory(machine, 8, (machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_S_signed as i64) as usize, machine.int_reg.get_reg(inst.rs2 as usize) as u64); }, _ => { panic!("In ST switch case, this should never happen... Instr was {}", inst.value); @@ -288,22 +276,22 @@ impl Machine { RISCV_OPI => { match inst.funct3 { RISCV_OPI_ADDI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] + inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) + inst.imm12_I_signed as i64); }, RISCV_OPI_SLTI => { - machine.int_reg[inst.rd as usize] = (machine.int_reg[inst.rs1 as usize] < inst.imm12_I_signed as i64) as i64; + machine.int_reg.set_reg(inst.rd as usize, if machine.int_reg.get_reg(inst.rs1 as usize) < inst.imm12_I_signed as i64 { 1 } else { 0 } ); }, RISCV_OPI_XORI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] ^ inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) ^ inst.imm12_I_signed as i64); }, RISCV_OPI_ORI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] | inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) | inst.imm12_I_signed as i64); }, RISCV_OPI_ANDI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] & inst.imm12_I_signed as i64; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) & inst.imm12_I_signed as i64); }, RISCV_OPI_SLLI => { - machine.int_reg[inst.rd as usize] = machine.int_reg[inst.rs1 as usize] << inst.shamt; + machine.int_reg.set_reg(inst.rd as usize, machine.int_reg.get_reg(inst.rs1 as usize) << inst.shamt); }, RISCV_OPI_SRI => { if inst.funct7_smaller == RISCV_OPI_SRI_SRLI { diff --git a/src/simulator/mod.rs b/src/simulator/mod.rs index 6aef6be..266e97a 100644 --- a/src/simulator/mod.rs +++ b/src/simulator/mod.rs @@ -167,7 +167,7 @@ pub mod global { /// /// Store doubleword (SD) (64 bits) /// - /// `SD rs2, imm12(rs1` => `rs2 -> mem[rs1 + imm12]` + /// `SD rs2, imm12(rs1)` => `rs2 -> mem[rs1 + imm12]` pub const RISCV_ST_STD: u8 = 0x3; /// Type: I