50 lines
1.5 KiB
Ruby
50 lines
1.5 KiB
Ruby
module Risc
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def self.operators
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[:+, :-, :>>, :<<, :*, :&, :|]
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end
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# Operator instructions on the first two registers given
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# # Result into the last register
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#
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# result = left OP right
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#
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# With OP being the normal logical and mathematical operations provided by
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# cpus. Ie "+" , "-", ">>", "<<", "*", "&", "|"
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#
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# Result may be nil, then register is autogenerated
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#
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class OperatorInstruction < Instruction
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def initialize( source , operator , left , right , result = nil)
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super(source)
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operator = operator.value if operator.is_a?(Sol::Constant)
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@operator = operator
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raise "unsuported operator :#{operator}:#{operator.class}:" unless Risc.operators.include?(operator)
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@left = left
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@right = right
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raise "Not register #{left}" unless left.is_a?(RegisterValue)
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raise "Not register #{right}" unless right.is_a?(RegisterValue)
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unless result
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result = RegisterValue.new("op_#{operator}_#{object_id.to_s(16)}".to_sym , :Integer)
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end
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raise "Not register #{result}" unless result.is_a?(RegisterValue)
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@result = result
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end
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attr_reader :operator, :left , :right , :result
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# return an array of names of registers that is used by the instruction
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def register_attributes
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[:left , :right, :result]
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end
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def to_s
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class_source "#{left} #{operator} #{right}"
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end
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end
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def self.op( source , operator , left , right , result = nil)
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OperatorInstruction.new( source , operator , left , right , result)
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end
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end
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