Torsten Ruger 633e99466d start to debug		2018-03-26 13:43:26 +03:00
..
interpreter	also separate risc and cpu inits for the machine	2018-03-25 19:36:00 +03:00
helper.rb	rename register to risc	2017-01-19 09:02:29 +02:00
test_assembler.rb	start to debug	2018-03-26 13:43:26 +03:00
test_collector.rb	rename register to risc	2017-01-19 09:02:29 +02:00
test_compat.rb	rename register to risc	2017-01-19 09:02:29 +02:00
test_instructions.rb	use common list for risc instruction	2018-03-18 10:36:01 +05:30
test_machine.rb	rename register to risc	2017-01-19 09:02:29 +02:00
test_padding.rb	rename register to risc	2017-01-19 09:02:29 +02:00
test_positioned.rb	rename register to risc	2017-01-19 09:02:29 +02:00
test_translator.rb	really translate risc - cpu/arm	2018-03-25 19:38:59 +03:00