Torsten Ruger
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3090ccffea
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keep risc and cpu instructions separate in method
that overwriting was a bit of thorn
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2018-03-25 19:33:50 +03:00 |
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Torsten Ruger
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793fa313a5
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change operators to symbols
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2018-03-24 17:53:27 +02:00 |
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Torsten Ruger
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2c137e8c97
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div10 test for interpreter
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2018-03-24 12:21:46 +02:00 |
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Torsten Ruger
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0f183b3a74
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fix value return and test
slot load was wrong way around
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2018-03-23 20:02:17 +02:00 |
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Torsten Ruger
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472b1a638a
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add register logging and fix function return
return semantics used to be different, now only register is given
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2018-03-23 18:56:38 +02:00 |
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Torsten Ruger
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34903829ca
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fix interpreter test harness and start testing
interpreter on debug for now
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2018-03-22 18:54:40 +02:00 |
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Torsten Ruger
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b4489b1093
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rename RiscTransfer to Transfer
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2018-03-21 15:48:04 +05:30 |
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Torsten Ruger
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aa79e41d1c
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rename register to risc
seems to fit the layer much better as we really have a very reduced
instruction set
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2017-01-19 09:02:29 +02:00 |
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