Torsten Ruger
294f4d988f
automatically create binary once cpu instructions are there
2018-03-26 19:42:15 +03:00
Torsten Ruger
e61ef93943
cleanup
2018-03-26 19:17:30 +03:00
Torsten Ruger
46a5eefbd4
reorder methods as they are called
2018-03-26 18:18:25 +03:00
Torsten Ruger
25c5b6dbbd
do or do not, there is not try
2018-03-26 18:14:39 +03:00
Torsten Ruger
1e21177b35
just keep binary code payload at 13 for now
...
there is an extra in there at the last of the last, but ok
2018-03-26 14:37:55 +03:00
Torsten Ruger
633e99466d
start to debug
2018-03-26 13:43:26 +03:00
Torsten Ruger
865a116f47
small assembler fix
2018-03-25 20:02:51 +03:00
Torsten Ruger
3bd23cee28
also separate risc and cpu inits for the machine
...
interpreter works on risc, but assembler off cpu
2018-03-25 19:36:00 +03:00
Torsten Ruger
a50368c3aa
assembler will need redoing somewhat
...
with own data objects, we can assemble into them first
then write
may also store cpu instructions
2018-03-25 18:23:00 +03:00
Torsten Ruger
fcbdba4804
simplify method entry exit codes
...
Basically just a label now
No more implicit returns (needs compiler tests)
Many return points is the new idea
Also setup is done before the enter by MessageSetup
2018-03-21 16:02:46 +05:30
Torsten Ruger
ba304f51df
using sof again, now rxf
2017-10-05 16:41:45 +03:00
Torsten Ruger
aa79e41d1c
rename register to risc
...
seems to fit the layer much better as we really have a very reduced
instruction set
2017-01-19 09:02:29 +02:00
