Torsten Ruger
3ceb2c2f69
fix div10 return sequence
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did not return at all before
2018-03-24 16:51:26 +02:00
Torsten Ruger
267237b776
fix init method message setup
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was causing errors in interpreter
(that may have gone unnoticed in arm, as the interpreter checks stuff)
2018-03-24 15:59:54 +02:00
Torsten Ruger
65d3d5f1c9
fix tests from interpreter load change
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loading values, not Constants
2018-03-24 12:24:53 +02:00
Torsten Ruger
2c137e8c97
div10 test for interpreter
2018-03-24 12:21:46 +02:00
Torsten Ruger
0f183b3a74
fix value return and test
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slot load was wrong way around
2018-03-23 20:02:17 +02:00
Torsten Ruger
c51e593335
test return in interpreter
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passes but does not return. dodgy
2018-03-23 11:36:20 +02:00
Torsten Ruger
55832315eb
more fix for multilevel constant load
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was ignoring first level which is already the second for a constant
as the constant is the first load.
first interpreter test working but looking dodgy
2018-03-22 19:14:22 +02:00
Torsten Ruger
34903829ca
fix interpreter test harness and start testing
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interpreter on debug for now
2018-03-22 18:54:40 +02:00
Torsten Ruger
b4489b1093
rename RiscTransfer to Transfer
2018-03-21 15:48:04 +05:30
Torsten Ruger
9989cc12e0
fix ass tests
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bit weak really, but pass
2018-03-18 22:37:15 +05:30
Torsten Ruger
c5ec532616
use common list for risc instruction
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strange that that was not done before as the code was clearly copied
when extracting it
Fix bug for insertion
2018-03-18 10:36:01 +05:30
Torsten Ruger
5fe0ba06ab
stash old vm
...
moving on to getting mom to work and can’t have both
interpreter and elf broke, about 100 tests went
2018-03-11 17:02:42 +05:30
Torsten Ruger
73b7e2b22f
remove all test_all
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Stop manually creating the list of tests (and searching missing).
Main level test_all does a search for all test_*
also possible to run by command line with starts
2017-04-13 17:00:56 +03:00
Torsten Ruger
0d96f5e35f
rearranges test helper modules
2017-04-10 16:12:15 +03:00
Torsten Ruger
ffbe39d571
order test requires
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easier to spot missed tests (when guard and cmd-line differ)
2017-04-02 22:42:51 +03:00
Torsten Ruger
aa79e41d1c
rename register to risc
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seems to fit the layer much better as we really have a very reduced
instruction set
2017-01-19 09:02:29 +02:00
