Convert SimpleCall to new regs

Also fix bug in RegsiterValue/Slot with chain, where logic was dodgy and compiler not set
This commit is contained in:
2020-03-01 23:38:23 +02:00
parent 4b303977a7
commit ff49ff50c0
8 changed files with 54 additions and 23 deletions

View File

@ -94,8 +94,7 @@ module Risc
# add the instruction to the code and return the register_value that was created
# for further use
def load_object( object )
raise "must be Parfait, not #{object.class}" unless object.is_a?(Parfait::Object)
ins = Risc.load_constant("load to #{object.type}" , object)
ins = Risc.load_constant("load to #{object}" , object)
ins.register.set_compiler(self)
add_code ins
# todo for constants (not objects)

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@ -33,9 +33,12 @@ module Risc
end
end
def self.load_constant( source , constant )
if(constant.is_a?(Parfait::Object))
value = constant
case constant
when Parfait::Object
type = constant.get_type
value = constant
when Label
type = constant.address.get_type
else
type = constant.ct_type
value = constant.value

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@ -40,15 +40,16 @@ module Risc
# Example: message[:caller][:next_message]
# message[:caller] returns a RegisterSlot, which would be self for this example
# to evaluate self[:next_message] we reduce self to a register with to_reg
def [](index)
def []( index )
reg = to_reg("reduce #{@register.symbol}[@index]")
reg[index]
end
# push the given register into the slot that self represents
# ie create a slot_to_reg instruction and add to the compiler
# the register represents and "array", and the content of the
# given register from, is pushed to the memory at register[index]
def to_mem(source , from )
def to_mem( source , from )
reg_to_slot = Risc.reg_to_slot(source , from , register, index)
compiler.add_code(reg_to_slot) if compiler
reg_to_slot.register
@ -57,9 +58,12 @@ module Risc
# load the conntent of the slot that self descibes into a a new register.
# the register is created, and the slot_to_reg instruction added to the
# compiler. the return is a bit like @register[@index]
def to_reg(source )
def to_reg( source )
slot_to_reg = Risc.slot_to_reg(source , register, index)
compiler.add_code(slot_to_reg) if compiler
if compiler
compiler.add_code(slot_to_reg)
slot_to_reg.register.set_compiler(compiler)
end
slot_to_reg.register
end

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@ -143,8 +143,8 @@ module Risc
when RegisterValue
ins = Risc.transfer("#{right.type} to #{self.type}" , right , self)
when RegisterSlot
raise "logic error, after creating the reg, need to transfer"
ins = Risc::SlotToReg.new("#{right.register.type}[#{right.index}] -> #{self.type}" , right.register , right.index , self)
index = right.register.resolve_index(right.index)
ins = SlotToReg.new("#{right.register.type}[#{right.index}] -> #{self.type}" , right.register , index , self)
else
raise "not implemented for #{right.class}:#{right}"
end