fix get_internal_byte

improved operators and tests
some logic errors still
This commit is contained in:
2020-03-09 12:47:12 +02:00
parent a70f63e7bb
commit fb4fa598f2
9 changed files with 46 additions and 45 deletions

View File

@ -72,6 +72,7 @@ module Risc
# from itself (the slot) and the register given
def <=( reg )
raise "not reg #{reg}" unless reg.is_a?(RegisterValue)
raise "Index must be register #{index}" unless(index.is_a?(RegisterValue))
reg_to_byte = Risc.reg_to_byte("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg , register, index)
compiler.add_code(reg_to_byte) if compiler
reg_to_byte

View File

@ -162,6 +162,7 @@ module Risc
# since << covers all other cases, this must have a RegisterSlot as the right
def <=( right )
raise "not implemented for #{right.class}:#{right}" unless right.is_a?( RegisterSlot )
raise "Right index must be register #{right.index}" unless(right.index.is_a?(RegisterValue))
ins = Risc.byte_to_reg("#{right.register.type}[#{right.index}] -> #{self.type}" , right.register , right.index , self)
compiler.add_code(ins) if compiler
return ins