fix get_internal_byte
improved operators and tests some logic errors still
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@ -72,6 +72,7 @@ module Risc
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# from itself (the slot) and the register given
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def <=( reg )
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raise "not reg #{reg}" unless reg.is_a?(RegisterValue)
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raise "Index must be register #{index}" unless(index.is_a?(RegisterValue))
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reg_to_byte = Risc.reg_to_byte("#{reg.class_name} -> #{register.class_name}[#{index}]" , reg , register, index)
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compiler.add_code(reg_to_byte) if compiler
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reg_to_byte
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@ -162,6 +162,7 @@ module Risc
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# since << covers all other cases, this must have a RegisterSlot as the right
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def <=( right )
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raise "not implemented for #{right.class}:#{right}" unless right.is_a?( RegisterSlot )
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raise "Right index must be register #{right.index}" unless(right.index.is_a?(RegisterValue))
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ins = Risc.byte_to_reg("#{right.register.type}[#{right.index}] -> #{self.type}" , right.register , right.index , self)
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compiler.add_code(ins) if compiler
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return ins
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